Commit Graph

58 Commits (6551672ce590650ebd485b1751df6e0ce7234bb5)

Author SHA1 Message Date
Rejeesh Kutty 8839c8b18c xfer-logic: stretch toggles to allow capture 2015-02-06 22:07:00 -05:00
Rejeesh Kutty 8050a14bd8 xfer-logic: stretch toggles to allow capture 2015-02-06 22:06:56 -05:00
Rejeesh Kutty b65bcab8d6 up_clkgen: reading typo 2015-01-07 13:58:43 -05:00
Rejeesh Kutty c3529f112f up_gt: move status to up clock 2014-12-19 13:00:27 +02:00
Lars-Peter Clausen 6197563506 up_axi: Fix up_raddr/up_waddr port width
Make sure that the port declaration width matches with the reg declaration
later on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
Rejeesh Kutty a4724f8396 es: added kcu105 gth 2014-11-17 09:55:12 -05:00
Rejeesh Kutty b1c91fac92 es: added kcu105 gth 2014-11-17 09:55:10 -05:00
Istvan Csomortani c6df568a00 Revert "ad_interrupts: Initial check in."
This reverts commit b254380338.
2014-11-06 12:16:52 +02:00
Rejeesh Kutty 74ec396b27 ad_rst: ultrascale -dual stage 2014-11-05 16:47:41 -05:00
Rejeesh Kutty 17cb1d9585 common/mem: asymmetric version 2014-10-30 11:12:09 -04:00
Istvan Csomortani b254380338 ad_interrupts: Initial check in.
Initial check in of the interrupt concatenation block.
2014-10-27 19:34:34 +02:00
Rejeesh Kutty 7e52cf9568 up_axi: timeout generating multiple/repeated acks 2014-10-23 13:51:33 -04:00
Adrian Costina 1d26639d73 common: Added synchronization mechanism to the up_adc_common module 2014-10-22 10:05:55 +03:00
Rejeesh Kutty 2817ccdb22 up_axi: altera can not handle same clock assertion of arready and rvalid 2014-10-09 15:25:05 -04:00
Adrian Costina 2dfcb0c599 usdrx1: Initial commit for a5gt
axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
Istvan Csomortani bfa17844ff ad_serdes_in: General update
Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
Rejeesh Kutty de33722470 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
Istvan Csomortani 079ed0ffb3 ad_serdes_in: Update the serdes_in module
Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
Istvan Csomortani 27ffff827a common: Initial check in of ad_serdes_in.v
A generic serdes module for input interface, support both 6 and 7 series.
2014-09-24 18:34:40 +03:00
acostina 5af2474d51 usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization 2014-09-23 22:44:33 -04:00
Lars-Peter Clausen b877cea2ed up_axi: Add parameter to configure the internal address width
Not all peripherals need 14 bit of address space.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:40 +02:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Lars-Peter Clausen 6ad589475a up_axi: Prevent read and write requests from racing against each other
Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.

This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:04:05 +02:00
Lars-Peter Clausen 18a506b3ca up_axi: Wait for the transaction to fully finish before releasing up_axi_access
Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.

This fixes problems in case the master is not ready to accept the response
when we make it available.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:03:52 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Adrian Costina a773cc4992 usdrx1: updated project
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
Istvan Csomortani 2b15c7313e ad_dcfilter: Fix filter loopback 2014-08-12 14:42:10 +03:00
Rejeesh Kutty 701dc96016 up_dac_channel: make iq cor coeff(s) tc 2014-07-24 10:10:24 -04:00
Istvan Csomortani db1c931736 ad9625_plddr: PL DDR3 fixes
- Modified the axi slave interface handler
  - Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
Rejeesh Kutty 2955b9db78 fifo2s: flush if no request, c5soc: 14.0 2014-07-15 16:25:33 -04:00
Rejeesh Kutty e7d5d79e42 daq2/kcu105: gth up and running - as it is commit 2014-07-10 10:56:37 -04:00
Rejeesh Kutty a9992f02b0 fifo2s: bug fixes- on 64mhz dma clock 2014-07-08 16:57:44 -04:00
Rejeesh Kutty a388ccab0a fmcomms2/c5soc: initial checkin 2014-07-02 14:56:00 -04:00
Rejeesh Kutty 60dd14bcdb a5soc: removed jtag master control 2014-07-01 12:27:37 -04:00
Rejeesh Kutty b6052773b7 added adc/dac gpio registers 2014-06-27 14:45:58 -04:00
Rejeesh Kutty 6b3312bbf9 library: register map changes and for mathworks 2014-06-24 14:24:22 -04:00
Rejeesh Kutty d4be46cc17 library: register map changes and for mathworks 2014-06-24 14:23:56 -04:00
Rejeesh Kutty cf56a568c6 kcu105: GTH updates 2014-06-05 14:27:38 -04:00
Rejeesh Kutty 842cd98b61 ad9361: adc loopback option 2014-05-27 12:15:02 -04:00
Rejeesh Kutty 0cd43e34f5 dds: zero scale fix 2014-05-21 11:54:49 -04:00
Rejeesh Kutty 3aed3ba71c axi_ad9361: fmcomms5 changes 2014-05-19 12:41:12 -04:00
Rejeesh Kutty f3f8374c75 ad9671: 2lane version 2014-05-08 18:33:26 -04:00
Rejeesh Kutty 5f2fb45b24 library: ported hdmi tx to altera 2014-05-02 12:07:47 -04:00
Rejeesh Kutty 503096de18 gt: change userready on drp clock 2014-04-17 16:09:55 -04:00
U-ANALOG\ACostina c73390b6c9 axi_ad9361: Intermediary check in for altera porting
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
Lars-Peter Clausen 799d2384d8 up_xfer_cntrl: Remove extra semicolon
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Rejeesh Kutty f8f2684b7e up_gt: eyescan delay bug fix 2014-04-02 16:45:41 -04:00
Rejeesh Kutty 2472d61daf ad_gt_es: status asserted early for latency 2014-04-01 15:06:51 -04:00
Rejeesh Kutty 724bd70a06 altera additions and replacements 2014-04-01 11:18:10 -04:00
Rejeesh Kutty 25f416e46f dds output is reset if disabled 2014-03-31 10:01:49 -04:00