Istvan Csomortani
|
3a0d1282b7
|
Fix the remaining issues
- Swap the IO locations of ports vsync and hsync
- Change the mem_interconnect optimization strategy to Maximize
Performance
|
2014-03-20 14:36:01 +02:00 |
|
Istvan Csomortani
|
7cdab9b5b0
|
Change the internal clock generator to Clock Wizard
- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
generation.
|
2014-03-18 17:24:45 +02:00 |
Rejeesh Kutty
|
dc44703cf1
|
zynq/non-zynq: identical signal names and instances
|
2014-03-17 17:02:03 -04:00 |
|
Rejeesh Kutty
|
a6da4ca01c
|
zynq/non-zynq merge variables
|
2014-03-17 16:39:52 -04:00 |
|
Rejeesh Kutty
|
e1f23e7d49
|
Merge branch 'master' of github.com:analogdevicesinc/hdl
|
2014-03-11 09:58:34 -04:00 |
|
Rejeesh Kutty
|
f3ae57a53e
|
global clock and reset names
|
2014-03-11 09:57:59 -04:00 |
|
Istvan Csomortani
|
75963ab376
|
Initial check in of VC707 base project
- All source files for the VC707 base project
- Update the common base system to the new naming convention
|
2014-03-10 17:26:17 +02:00 |
|
Rejeesh Kutty
|
5c3b65d01b
|
adv7511: kc705/ac701 updates
|
2014-03-06 09:36:50 -05:00 |
|
Rejeesh Kutty
|
360f10395a
|
initial checkin
|
2014-03-03 13:42:25 -05:00 |
|
Rejeesh Kutty
|
3c0ea759a0
|
changed path settings
|
2014-03-03 10:06:02 -05:00 |
|
Rejeesh Kutty
|
ddac1a8834
|
added common board files
|
2014-02-28 21:17:01 -05:00 |