Commit Graph

3814 Commits (6649b23bc885410b59b11e9c128bd76225dfa918)

Author SHA1 Message Date
AndreiGrozav d6b09602ed usrpe31x: Automatic IP version update 2017-05-02 12:27:57 +03:00
AndreiGrozav 485c810c2c pzsdr*: Automatic IP version update 2017-05-02 11:43:32 +03:00
Rejeesh Kutty b3ce821311 change pl ddr clock to 1G 2017-05-01 09:35:10 -04:00
Rejeesh Kutty d29f420ffa axi_fmcadc5_sync: add a calibration signal generation 2017-04-28 11:13:24 -04:00
Lars-Peter Clausen 7a53b99b8b daq2: zc706: Increase DAC FIFO size
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.

In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 12:29:01 +02:00
Istvan Csomortani f6eea23f5e adaq7980: Update tcl command for IP configuration 2017-04-28 10:12:33 +03:00
Istvan Csomortani 353d1d44da ad5766_sdz: Update tcl commands for IP configuration 2017-04-28 10:12:05 +03:00
Rejeesh Kutty 956753ca9c hdlmake- updates 2017-04-27 15:11:01 -04:00
Rejeesh Kutty 68fc5c89a7 fmcadc5- remove stand alone psync 2017-04-27 15:09:56 -04:00
Rejeesh Kutty 75c7525c60 fmcadc5- remove psync module 2017-04-27 13:29:06 -04:00
Rejeesh Kutty 2027c8427c adi_boadr- disconnect and remove unused ports 2017-04-27 13:26:17 -04:00
Rejeesh Kutty 902eaaaf4c fmcadc5- sync updates 2017-04-27 13:26:17 -04:00
Rejeesh Kutty 0cb2316cb9 fmcadc5-sync- add ldo psync 2017-04-27 13:26:17 -04:00
Istvan Csomortani 0442e7d404 util_adxcvr: Fix parameter setup at instantiation
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
2017-04-27 15:35:39 +03:00
Istvan Csomortani 49ef9a589b axi_ad5766: Fix parameter name for up_dac_common 2017-04-27 13:55:16 +03:00
Istvan Csomortani 8aa8d3a0e5 ad5766_sdz/zed: Fix i_iobuf_reset width 2017-04-27 11:28:26 +03:00
Istvan Csomortani 4e15a21b79 spi_engine_interconnect: Delete dependency defined for S1_CTRL interface
The S1_CTRL interface is not dependent of the number of SDI lines.
2017-04-27 11:28:25 +03:00
Istvan Csomortani 4ceed4d373 util_pulse_gen: Add Makefile 2017-04-27 11:28:25 +03:00
Istvan Csomortani 4836aa2179 adaq7980/zed: Update Makefile 2017-04-27 11:28:25 +03:00
Istvan Csomortani 18a671cdb7 spi_engine: Expose DATA_WIDTH to software
The value of DATA_WIDTH can be read back from register 0x44
The DATA_WIDTH will define the size of a word in a transaction.
2017-04-27 11:28:24 +03:00
Istvan Csomortani 801fb2281e util_pulse_gen: The valid period is stored in pulse_period_d 2017-04-27 11:28:24 +03:00
Istvan Csomortani fbccb377cc adaq7980: Add an trigger generator for SPI offload 2017-04-27 11:28:23 +03:00
Istvan Csomortani 63cab50872 adaq7980_sdz: Initial commit
The device is interfaced with a SPI Engine, the PD lines are controlled
by GPIOs.
2017-04-27 11:28:23 +03:00
Istvan Csomortani a4c422ac4c spi_engine_execution: Define port dependencies for SDI ports 2017-04-27 11:28:21 +03:00
Istvan Csomortani 045cb96744 axi_spi_engine: Define ports dependencies for up_* interface
The up_* interface ports are active just if the MM_IF_TYPE is UP_FIFO.
2017-04-27 11:27:35 +03:00
Dragos Bogdan ccc4aac505 ad5766_sdz: Fix the PIN assignment 2017-04-27 11:27:34 +03:00
Istvan Csomortani 8213d8a916 cn0363: Update block design
Configure the interconnect and offload modules inorder to activate
its interfaces. In the past, these interfaces did not have any
parameter dependencies, so this configuration were not required.
2017-04-27 11:27:33 +03:00
Istvan Csomortani 9cd218eb90 up_dac_common: Increase datawidth of dac_datarate
In case of high precision devices with just a simple SPI interface
for control and data, the effective data rate can be significatly
lower than the SPI clock, and more importantly there isn't any relation
between the two clock domain.
The rate is defined by a SOT (start of transfer) generator, which
initiates a SPI transfer. Taking the fact that the generator runs
on system clock (100 MHz), and the device can require smaller rate (in kHz domain),
the 7 bit dac_datarate register is just too small.

Therefor increasing to 16 bit.
2017-04-27 11:24:08 +03:00
Istvan Csomortani a6146393be ad5766_sdz: Fix DMA data path 2017-04-27 11:22:32 +03:00
Istvan Csomortani a2c20551a2 axi_ad5766: Add Makefiles for the core 2017-04-27 11:22:31 +03:00
Istvan Csomortani eba22892b8 axi_ad5766: Preserve consistent coding style 2017-04-27 11:21:15 +03:00
Istvan Csomortani f5fba79a08 ad5766_zed: Add an IOBUF to the reset line 2017-04-27 11:21:14 +03:00
Istvan Csomortani 9de0fe56d9 ad5766: Integrate the new axi_ad5766 into the project 2017-04-27 11:21:14 +03:00
Istvan Csomortani d061104a3c util_pulse_gen: Add configuration interface for 'pulse period'. 2017-04-27 11:21:12 +03:00
Istvan Csomortani 825d46259b interface: Update spi_engine_offload_ctrl definition
Because of the new AD5766 offload module, SDO lines are
defined as 'optional'.
2017-04-27 11:19:22 +03:00
Istvan Csomortani 5c5baf3abf spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s should be used,
when cmd_fifo_in_valid is generated.
2017-04-27 11:19:20 +03:00
Istvan Csomortani 29f0ce36bb axi_ad5766: Initial commit
This core can be used in conjunction with the SPI_ENGINE, will work
as an offload module, forwarding a data stream to the SPI excecution,
received from a DMA.
2017-04-27 11:16:23 +03:00
Istvan Csomortani d177827224 ad5766_sdz : Fix SPI interface connection 2017-04-27 11:16:23 +03:00
Istvan Csomortani fb6e0d3efb spi_engine: Add dependency for unused interfaces 2017-04-27 11:16:19 +03:00
Istvan Csomortani 225d133a68 ad5766_sdz: Initial commit 2017-04-27 11:12:45 +03:00
Rejeesh Kutty 5d6b018b2b ad9162- add iq swap 2017-04-26 20:54:47 -04:00
Istvan Csomortani 85a647eda8 axi_ad9361: Fix ad_cmos_out instantiations
This is a patch for 3627b89
2017-04-26 10:39:54 +03:00
Adrian Costina 7cff12107e hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile 2017-04-26 09:58:17 +03:00
Rejeesh Kutty cfd4e006b3 hdlmake updates 2017-04-25 15:46:26 -04:00
Rejeesh Kutty 8fba8295f0 fmcadc5- hdl sync handling 2017-04-25 15:44:40 -04:00
Rejeesh Kutty 68bb7ffa40 adi_board- keep port delete simple 2017-04-25 15:44:03 -04:00
Rejeesh Kutty 804df251a6 axi_fmcadc5_sync- updates 2017-04-25 11:35:37 -04:00
Rejeesh Kutty 81570ada75 axi_fmcadc5_sync- updates 2017-04-25 11:35:37 -04:00
Rejeesh Kutty c248d5ac6a fmcadc5-sync- try sync in hdl 2017-04-25 11:35:37 -04:00
Istvan Csomortani 8eb65186e9 cn0363: Reorder the configuration settings of the fir filters
It seems that there are some dependencies between the fir compiler
cores parameters. With the old order of the parameter settings,
the tool throws the following warning:

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES
does not match between /processing/sequencer/i_q_filtered(4)
and /processing/lpf/M_AXIS_DATA(5)
2017-04-25 17:40:09 +03:00