Commit Graph

1607 Commits (669e0a01d0cda4f70bcd9558e8a6284bd465cf9d)

Author SHA1 Message Date
Istvan Csomortani 10898d6618 constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
Istvan Csomortani cb8d6830f5 avl_dacfifo: Update constraints 2017-05-25 15:12:16 +03:00
Istvan Csomortani 3ee7ed7375 avl_dacfifo: Cosmetic changes 2017-05-25 15:12:15 +03:00
Istvan Csomortani 154e936a4b avl_dacfifo: Fix issues with avl_dacfifo_wr
+ fix issues with the last partial avalon transfer.
 + fix reset related problems
2017-05-25 15:12:15 +03:00
Istvan Csomortani e34e87e7f8 avl_dacfifo: Add support for partial avalon transfers
By adding support for partial avalon transfers (data width < bus width),
valid data set size (DMA transfer length) will be dependent on the DMA bus
width only.
2017-05-25 15:12:15 +03:00
Istvan Csomortani a993eefe57 avl_dacfifo: Grey coder/decoder integration 2017-05-25 15:12:14 +03:00
Istvan Csomortani 0bf6a37bd0 common: Add grey coder and decoder modules 2017-05-25 15:12:14 +03:00
Istvan Csomortani 14a058195d avl_dacfifo: Add avl_dacfifo_byteenable_coder
Define and integrate avl_dacfifo_byteenabke_coder module,
which generates the byteenable signal for the avalon interface.
2017-05-25 15:12:14 +03:00
Istvan Csomortani 81fa65cd51 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
+ avl_write_transfer_done_s is a redundant net
 + specify the net state explicitly on if statements
 + to define the edge of avl_mem_fetch_wr_address signal,
its register and its second sync register should be used
2017-05-25 15:12:13 +03:00
Istvan Csomortani 398619d866 avl_dacfifo: Add support for MEM_RATIO 32 2017-05-25 15:12:13 +03:00
Istvan Csomortani a1539a62b7 avl_dacfifo: Integrate util_delay into dac_xfer_out path
The ad_mem_asym memory read interface has a 3 clock cycle delay, from the
moment of the address change until a valid data arrives on the bus;
because the dac_xfer_out is going to validate the outgoing samples (in conjunction
with the DAC VALID, which is free a running signal), this module will compensate
this delay, to prevent duplicated samples in the beginning of the
transaction.
2017-05-25 15:12:13 +03:00
Istvan Csomortani 6d52034abb avl_dacfifo: dma_ready was muxed incorrectly 2017-05-25 15:12:12 +03:00
Istvan Csomortani da68705fee avl_dacfifo: Fix the avalon address switch 2017-05-25 15:12:12 +03:00
Istvan Csomortani 04f397f688 avl_dacfifo: Fix a few control signals
+ avl_last_transfer depends on the avl_xfer_req state
  + avl_xfer_req will be asserted after the last avalon write
transfer
2017-05-25 15:12:12 +03:00
Istvan Csomortani 8f9cadb017 avl_dacfifo: Fix the avl_write generation
The asymetric memory has a 3 clock cycle delay on its read
interface, therefor the minimum distance between two consecutive
avalon write should be 3.
2017-05-25 15:12:11 +03:00
Istvan Csomortani 0f1e51ac98 avl_dacfifo: Fix alv_mem_readen generation 2017-05-25 15:12:11 +03:00
Istvan Csomortani f456ebc6f0 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
+ all net names should have a *_s postfix
  + avl_burstcount is a constant 1, no need for an additional
register for it
  + all CDC should have two synchronization register, add
avl_last_beat_req_m2
2017-05-25 15:12:11 +03:00
Istvan Csomortani 6ea87d094e util_delay: Initial commit
Generic module to introduce a fix N cycle delay into a datapath.
2017-05-25 15:12:10 +03:00
Istvan Csomortani 9a6dc36289 avl_dacfifo: Fix indentation for acl_dacfifo.v 2017-05-25 15:12:10 +03:00
Istvan Csomortani 7666c9f0d2 avl_dacfifo: Add a parameter AVL_ADDRESS_WIDTH 2017-05-25 15:12:10 +03:00
Istvan Csomortani 6dbbe2f1ca altera/ad_mem_asym: Fix grounded bus for marco instance
The "'b0" constant will be translate as a 32 bit width vector by
ModelSim, and will throw a buswidth mismatch error. Tie the data_b
bus to zero, using its width parameter.
2017-05-25 15:12:09 +03:00
Lars-Peter Clausen d883aabcc1 adi_ip.tcl: Use analog.com for interface vendor
Currently the scripts use 'analog.com' as the vendor property for IP cores,
but 'ADI' for interfaces.

Make things consistent by using 'analog.com' for both interfaces as well
as IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:10:15 +02:00
Lars-Peter Clausen 7020f94968 interfaces: Add dependencies to rule
Make sure that the XML files are re-build when any of the scripts that are
used to generated it are modified.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:10:15 +02:00
Lars-Peter Clausen 5ba1c4fef3 interfaces: Simplify Makefile
All the rules to generate the XML files are the same. Reduce the number of
rules by useing wildcard matching for the rule target.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:09:52 +02:00
Adrian Costina 229829e4dc axi_ad9963: Add scale only correction option 2017-05-24 15:55:45 +03:00
Adrian Costina c7df3e8ae9 ad_iqcor: Add scale only correction option 2017-05-24 15:54:58 +03:00
Rejeesh Kutty 0930c486d2 axi_hdmi_rx- move data to an iob 2017-05-19 16:25:54 -04:00
Lars-Peter Clausen 858065d49b library: Sort Makefile
Sort the entries in the library Makefile alphabetical. Keeping it ordered
makes it easier to track changes compared to randomly reshuffling it
every time a new entry is added.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
Rejeesh Kutty 393577c911 util_adxcvr- 2016.4 gthe4 updates 2017-05-18 14:49:18 -04:00
Rejeesh Kutty 80a3f45b9f alt_mul- qsys replacement 2017-05-18 10:38:48 -04:00
Rejeesh Kutty 598bd7e226 resolving conflicts 2017-05-17 16:18:53 -04:00
Rejeesh Kutty 6649b23bc8 alt-mem-asym - replace mega function cores 2017-05-17 16:13:26 -04:00
Rejeesh Kutty 828c2406cb adi-ip-alt allow changing device family 2017-05-17 16:13:26 -04:00
Rejeesh Kutty bea72232a3 alt_mem_asym- qsys component 2017-05-17 16:13:26 -04:00
Istvan Csomortani fe140a054f license: Fix VHDL license header 2017-05-17 18:28:06 +03:00
AndreiGrozav 70e3dd00ff scripts: Update required tool versions 2017-05-17 16:45:20 +03:00
Lars-Peter Clausen bf44f357fe Fix VHDL files license header, second try
While VHDL uses -- for comments uris still use //.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 15:25:08 +02:00
Lars-Peter Clausen 5ee9480142 Fix VHDL files license header
VHDL uses '--' for comments rather than '//'.

Also remove left over old license headers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 15:21:06 +02:00
AndreiGrozav 18bc5465df axi_usb_fx3: Add missing ports 2017-05-17 14:48:28 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
AndreiGrozav 857ad45d57 util_fir_int: Force 1/8 filter input data rate 2017-05-16 19:35:24 +03:00
AndreiGrozav 3f5d930cde axi_adc_decimate/cic_decim: Fix clk_enable warning
- fix clk_enable zero replication warning
2017-05-16 19:35:24 +03:00
AndreiGrozav fd7db4fcf3 util_tdd_sync: add missing ports 2017-05-16 19:35:24 +03:00
AndreiGrozav cf3737122b Remove duplicare wire declaration
-Introduced by updating to verilog-2001
2017-05-16 19:35:24 +03:00
AndreiGrozav 41e25e7c96 Add missing ad_serdes_out interface ports 2017-05-16 19:35:24 +03:00
Adrian Costina 0c5dabe358 axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed 2017-05-15 18:59:09 +03:00
Adrian Costina ce4f9bf906 up_dac_common: rename internal signals 2017-05-15 18:58:26 +03:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty ecfa15bfce version check- change to critical warning 2017-05-12 09:51:48 -04:00