* The version is set to be 23.2.0 because this is what Quartus returns
as value when running the --version command
* Still, Quartus has as installation path "intelFPGA_pro/23.2" and not
the version which contains an additional ".0"
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Recommend storing images like any other artifact: in a hierarchical
manner, without "images" subfolders.
This is intended to avoid dangling artifacts when projects are moved,
renamed, or deleted.
Recommend overwriting the page title with a shorter title in the
toctree, so the navigation bar doesn't overflow or get too cluttered.
Add acostina to CODEOWNERS
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
This commit makes the following changes:
Add SPI Engine for serial mode
Add SER_PAR_N build parameter, set default 1 for serial
Fix irq consistency in ad7616_bd.tcl
Fix regmap and offload names
Fix system_top.v GPIOs
* Projects: Add missing sysid IP
* Added make parameters for the sysid ip for the projects: ad9209_fmca_ebz/vck190, ad9213_dual_ebz/s10soc and adrv9009/s10soc
Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
Fixed wrong behaviour on chip select instruction:
- previously, a sleep time happened before the chip select change
- the intended behaviour was for another sleep time, of equal amount, to happen after the chip select change as well
- additionally, the counter logic implementation was creating an additional factor of 2 on the sleep time
All of the above points were fixed. The changes introduced also fix another issue where the sleep instruction was likewise happening with a duration larger than intended by a factor of 2
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Commit 5db7574 switched ad_cpu_interconnect from SmartConnect to
AXI Interconnect for Zynq-7000 family SoC. This commit does the
same for ad_mem_hpx_interconnect.
Signed-off-by: Alexander Vickberg <wickbergster@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* Created the template for the HDL project documentation
* Added the More information and Support pages as two separate files
which will be embedded in the project documentations
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
* Created the first level of pages for the User guide, from Analog Wiki:
* Architecture
* Build HDL
* Customize HDL
* Docs guidelines (edited)
* Git repository
* HDL coding guideline (edited)
* Introduction
* IP cores
* Porting projects (edited)
* Releases
* Third party
* Moved hdl_coding_guideline under user_guide and changed extension to rst
* Deleted hdl_pr_process.md
* docs_guideline: Add reference to project doc template
* porting_project:
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
* Remove sphinxcontrib.mermaid extension
* Added red and green role
* Fixed the :part: role link because analog.com doesn't know to
redirect to proper part webpage if it's under /products
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
I changed the comments from system_constr.xdc file.
Added pulsar_adc_pmdz_pmod.txt.
Tests were done on the eval-ad7689-ebz and eval-ad7984-pmdz boards.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update cn0363 spi engine
I replaced the SPI Engine connections in the cn0363_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I updated the system_constr.xdc file and
created the cn0363_pmod.txt file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update ad469x spi engine
I replaced the SPI Engine connections in the ad469x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I also created the ad469x_fmc.txt file for generating the
system_constr.xdc file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
* Update SPI Engine AD738x
I replaced the SPI Engine connections in the ad738x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I changed the ad738x_bd.tcl where it was added spi_engine_create
procedure, system_bd.tcl and system_top.v files.
I have update system_constr.xdc file and added ad738x_fmc.txt file.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
In this project it was created the ad5766_fmc.txt file for generating the system_constr.xdc file.
Also it was updated the system_constr.xdc and Readme.md files.
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
I replaced the SPI Engine connections in the adaq7980_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I configured the parameters for axi_pwm_gen and axi_clkgen according
to the results in the SPI_Engine_Timing_Computations Excel where I created a file
for adaq7980.
I created the adaq7980_fmc.txt file for generating the system_constr.xdc file.
I modified the system_bd.tcl, system_top.v, system_constr.xdc and Readme.md files.
Also I regenerated the Makefile.
Update docs instructions in the README.md to recommend building the libraries before generating the documentation.
Fix misspellings in the SPI Engines.
Use hashlib to gen the reproducible ids, so these elements won't be committed at every build in the gh-pages branch.
Get username from environment variable, to use in the symbolator local installation path, dismissing user interaction for this.
Use modelParameter to extract the type from ip-xact parameters without the format field, and improve formatting.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
This commit adds support for ADALM-PHASER, allowing the user to choose between the default PlutoSDR mode and Phaser mode
through a software controlled GPIO pin: phaser_enable.
The Generic TDD Engine was integrated to output a logic signal on the L10P pin, which connects to the input of the ADF4159,
when receiving an external synchronization signal on the L12N pin from the Raspberry Pi. Two additional TDD channels are used
to synchronize the TX/RX DMA transfer start:
- TDD CH1 is connected to the RX DMA, triggering the synchronization flag;
- TDD CH2 is connected to the TX unpacker's reset, backpressuring the TX DMA until deasserted.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with
buffered differential, wide common range picoamp inputs.
The design supports:
- CMOS and LVDS interfaces(at build time)
- Runtime sampling changes
- Store captured samples in RAM, through DMA (available via software support)
Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
The axi_ad4858 IP core is design as the HDL interface for the AD4858 ADC.
Features:
- AXI based configuration
- LVDS and CMOS support
- Configurable number of active data lines (CMOS - build-time configurable)
- Oversampling support
- Supports packet formats 0,1,2 or 3
- CRC check support
- Real-time data header access
- Channel based raw data access(0x0408)
- Xilinx devices compatible
Documentation at https://wiki.analog.com/resources/fpga/docs/axi_ad4858
The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC.
The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal.
If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS.
If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS.
The VADJ voltage should be set to 1.8V.
Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
The custom interface IP for AD3552R DAC has more operation capabilities:
- 8b register read/write SDR/DDR
- 16b register read/write SDR/DDR
- data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)
- selectable input source : DMA/ADC/TEST_RAMP
- data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode
- the IP reference clock (clk_in) can have a maximum frequency of 132MHz
- the IP has multiple device synchronization capability when the DMA is set as an input data source
Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
Stanca Pop
Iulia Moldovan
Jorge Marques
Ramon Cristopher Calam
Alin-Tudor Sferle
PIoandan
LBFFilho
kylex
Bogdan Luncan
Ioan-daniel Pop
laurentiu_popa
Vilmos-Csaba Jozsa
Liviu.Iacob
Ionut Podgoreanu
AndreiGrozav
PopPaul2021