d840baee28
util_clkdiv: Register output port as a clock ( #33 )
...
If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:52:43 +01:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
c637d848bb
util_clkdiv: constraints should be applied LATE for this core
2017-04-03 18:14:29 +03:00
61afd106b5
util_clkdiv: Keep as valid only settings common for 7Series and Ultrascale
2017-01-18 11:56:24 +02:00
61ee24f26a
util_clkdiv: Make the clock division parametrizable and changed C_SIM_DEVICE to SIM_DEVICE
2017-01-16 14:37:26 +02:00
4b2602437f
util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching
2017-01-13 13:54:07 +02:00
9b29941c77
util_clkdiv: Add constraint file
2017-01-11 18:11:53 +02:00
609b01f9e4
util_clkdiv: Added division by 2 option
2016-11-24 16:01:37 +02:00
c072c2f89a
util_clkdiv: Add IP
2016-09-30 17:13:51 +03:00
Matthew Fornero
Istvan Csomortani
Adrian Costina