692cb10fb2
ad9625- xcvr updates
2016-09-26 15:21:11 -04:00
751a66eb72
plddr3/zc706- board pin warning
2016-09-26 15:20:37 -04:00
79b9e21be8
board- xcvr procedure
2016-09-26 15:20:18 -04:00
8314efd4e9
fmcomms11- xcvr updates
2016-09-26 15:19:29 -04:00
7fd9280cbf
fmcomms11- xcvr updates
2016-09-26 15:19:05 -04:00
ad16aec101
axi_ad9684: Fix SERDES modules
2016-09-26 11:14:35 +03:00
f5809b8817
adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port
2016-09-24 10:09:05 +03:00
2d307d5f58
a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design
2016-09-24 10:06:35 +03:00
f6c7aa9005
library- dac parameter changes
2016-09-23 16:15:59 -04:00
1a11e28821
ad9361- dac data path split
2016-09-23 16:13:46 -04:00
6735333aea
common- dac data path split
2016-09-23 16:13:24 -04:00
6837143110
library/ adc parameter changes
2016-09-23 13:44:47 -04:00
7be6168b2e
ad9361- adc data path split
2016-09-23 13:42:14 -04:00
8729af1b91
common- adc- data path disable split
2016-09-23 13:40:35 -04:00
78f7384150
ad9361- vivado synthesis warnings fix
2016-09-22 13:41:18 -04:00
df37a23a48
pzsdr/ccfmc- rgmii critical warnings fix
2016-09-22 11:38:43 -04:00
dc6f7bbc4e
pzsdr/ccfmc - loopback updates
2016-09-22 11:18:13 -04:00
2b6eb1d65e
up_drp: Revert some bit locations
...
Linuxe drivers are checking the drp_locked status even if the
core does not contains a clock generation/managment module. To
not break all the designs, revert all the status and control bits to
there old locations.
2016-09-22 16:32:42 +03:00
0e2572bbd8
pzsdr- ccbrk_cmos- loopback changes
2016-09-21 13:16:04 -04:00
14ad1ea741
pzsdr- swap clear-up
2016-09-21 13:15:40 -04:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
143423e3b9
adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera
2016-09-21 18:13:02 +03:00
500d8bfb90
adrv9371x: A10GX, fix makefile and system_qsys.tcl script
2016-09-21 18:11:35 +03:00
79f34c9de7
ccbrk- test updates
2016-09-21 11:04:22 -04:00
a2e60cf693
ccbrk - test
2016-09-21 11:04:22 -04:00
0def596b43
axi_xcvrlb- updates
2016-09-21 11:04:22 -04:00
d497a7b0ae
axi_xcvrlb- constraints
2016-09-21 11:04:22 -04:00
a21b9fe8ff
up_drp: Fix up_drp_wr
2016-09-21 17:55:58 +03:00
64cd7dc002
axi_ad9122: Update core to the new DRP interface
2016-09-21 16:09:55 +03:00
bae839acd4
axi_ad9739a: Update core to the new DRP interface
2016-09-21 15:23:08 +03:00
781702c1b9
axi_ad9434: Update the core to the new DRP interface
2016-09-21 15:12:59 +03:00
913eafed48
up_drp : Update the DRP interface to support Altera platforms
2016-09-21 15:00:45 +03:00
10408b8c88
up_tdd_cntrl: Set PCORE version to 1.00.a
2016-09-21 10:27:28 +03:00
1860d72df6
axi_xcvrlb- updates
2016-09-19 12:39:59 -04:00
5592c2780e
axi_xcvrlb- loopback version
2016-09-19 12:39:59 -04:00
38f1521861
xilinx/ad_serdes_in : Fix some typos
2016-09-19 16:02:52 +03:00
ff0f659a33
xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE
2016-09-19 16:02:06 +03:00
3ca9fe0919
sdrstk- remove critical warnings from ps7
2016-09-16 14:06:12 -04:00
2159f78c80
axi_ad9361: Delete invalid assignment of a generated wire
2016-09-16 17:38:08 +03:00
f1e787f86b
fmcomms2: TDD control is enabled by default
2016-09-16 14:45:39 +03:00
6510f92c12
ad_serdes : Cosmetic changes
2016-09-16 14:45:39 +03:00
13a35f7a2a
altera/ad_serdes_clk: The IO_PLL reset is active heigh
2016-09-16 14:20:39 +03:00
858ea09048
altera/ad_serdes_in: Fix some typos
2016-09-16 10:56:16 +03:00
2a7bc31c01
pzsdr1- disable gpreg constraints
2016-09-15 13:49:04 -04:00
a2d15acb89
ad_serdes- altera/xilinx sync
2016-09-15 13:33:55 -04:00
67d4e71ff0
pzsdr1- disable gpreg constraints
2016-09-15 12:41:40 -04:00
63696c1a28
alt_serdes- data-width parameter
2016-09-15 11:12:18 -04:00
02dfd2d2e2
altera/ad_serdes_out- sample transmit order
2016-09-15 10:28:34 -04:00
5986f45cba
altera/ad_serdes_out- updates
2016-09-15 09:38:11 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Dragos Bogdan
AndreiGrozav