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3096 Commits (693c0026681a00e0632280ace7f132d133eefb20)

Author SHA1 Message Date
Laszlo Nagy 693c002668 ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR 
Remove Xilinx PHY and simplify project
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d92f925b06 ad9081_fmca_ebz: Disable XBAR from DAC TPL 2021-05-14 15:39:40 +03:00
Laszlo Nagy 77a5edaa83 scripts/adi_board.tcl: In 204C do not connect SYNC 
Take link mode parameter from util_adxcvr, check it against the axi_adxcvr.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 1db04a47b8 ad9083_evb: Update parameters to 10Gpbs lane rate 2021-04-19 13:21:34 +03:00
vladimirnesterov 8335e1bd9a sysid: Make sure gitbranch_string is always declared 
Parsing of not existed "gitbranch_string" fails the build process.
 2021-03-24 13:34:32 +02:00
Sergiu Arpadi 6a374ef457 ad469x/zed: Add multicycle path constraint 2021-03-22 13:05:05 +02:00
Sergiu Arpadi 40baa63f0f adrv2crr_fmcomms8: Fix system_top.v 2021-03-19 17:56:28 +02:00
Sergiu Arpadi a1773c661c adrv9009zu11eg_crr: Update spi 
Add two more CS signals to P25 connector
 2021-03-10 10:53:11 +02:00
sergiu arpadi 3dce87d09b ad9083: Add reference design for ad9083 eval board 2021-03-10 10:52:03 +02:00
Laszlo Nagy dcec4fe1b7 adrv9001/zc706: Fix spaces 2021-03-10 10:35:52 +02:00
Laszlo Nagy dc186645d8 adrv9001/zc706: Fix comments HPC to LPC 2021-03-10 10:35:52 +02:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0 
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
 2021-03-08 11:29:33 +02:00
Laszlo Nagy 1099badaf4 ad9082_fmca_ebz:zc706: Initial version 2021-03-05 15:54:23 +02:00
Laszlo Nagy 2213527f29 ad9082_fmca_ebz:zcu102: Initial version 2021-03-05 15:54:23 +02:00
Laszlo Nagy f56e3c305b ad9082_fmca_ebz:vcu118: Initial version 2021-03-05 15:54:23 +02:00
Laszlo Nagy 6b13b32f24 ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size 2021-03-04 11:13:29 +02:00
Laszlo Nagy 677c154134 adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings 
Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
 2021-03-04 11:13:10 +02:00
Laszlo Nagy 03de08609b fmcomms2/zed: Disable unused TDD to save space and timing 2021-03-04 11:13:10 +02:00
Laszlo Nagy 0dd3173547 adrv9001/zc706: Initial commit 
The project supports CMOS interface only.

VADJ on the ZC706 must be programmed to 1.8V
Instructions can be found here:
https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086
 2021-03-03 09:03:03 +02:00
Sergiu Arpadi 3be5137aec cn0540/cora: Remove multicycle constraint 
Design uses 80MHz spi_clk which does not require
special considerations
 2021-02-18 14:14:16 +02:00
Laszlo Nagy 701e5f6515 scripts/adi_board.tcl: Add simulation support 
This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.

Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller

Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
 2021-02-12 16:21:10 +02:00
Laszlo Nagy 0374a7c1ac ad9081_fmca_ebz/vcu118: Added common 204C use cases as example 2021-02-05 15:24:15 +02:00
Laszlo Nagy ddd8a14790 ad9081_fmca_ebz: Remove system reset from Xilinx PHY 
Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
 2021-02-05 15:24:15 +02:00
Laszlo Nagy af3e1c7003 ad9081_fmca_ebz/a10soc: Np 12 support 2021-02-05 15:24:15 +02:00
Laszlo Nagy f73ed741c9 fmcadc5: Connect link clock to second JESD link layer 2021-02-05 15:24:15 +02:00
Laszlo Nagy 3f2f88ebbc ad_fmclidar1_ebz: Set bits per sample towards the DMA interface 2021-02-05 15:24:15 +02:00
Laszlo Nagy dafdd1c1e9 ad9208_dual_ebz: Use ad_xcvrcon procedure to connect device clock 2021-02-05 15:24:15 +02:00
Laszlo Nagy bb9eafceef ad9081_fmca_ebz/zcu102: Add case analysis to select correct out clock frequency 2021-02-05 15:24:15 +02:00
Laszlo Nagy d0f8a81b2f ad9081_fmca_ebz: Np 12 support 
204B functional
204C functional
 2021-02-05 15:24:15 +02:00
Laszlo Nagy 454b900f90 jesd204: Xilinx: NP=12 support 
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.

e.g  Input datapath width = 4; Output datpath width = 6;
  for F=3 one beat contains 2 frames
  for F=6 one beat contains 1 frame

The width change is realized with a gearbox.

Due the interface width change the single clock domain core is split
in two clock domains.
  - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
  -              lane rate / 20 for input datapath width of 8 octets 8b10b
  -              lane rate / 66 for input datapath width of 8 octets 64b66b

  - Device clock : Link clock * input data path width / output datapath width

Interface to transport layer and SYSREF handling is moved to device clock domain.

The configuration interface reflects the dual clock domain.

If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
 2021-02-05 15:24:15 +02:00
Adrian Costina 7be66b63c1 adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8 2021-02-05 15:07:09 +02:00
Adrian Costina 6d504d14cf fmcomms8: zcu102: Fix lane swapping 2021-02-05 15:07:09 +02:00
Laszlo Nagy 0fd5590e56 ad9081_fmca_ebz: a10soc: Initial version 
Parametrizable project with default profile of:

  M=8 L=4 SampleRate=250 MSPS
  LaneRate=10 Gbps
 2021-02-05 10:24:59 +02:00
Laszlo Nagy 6e6c51dd27 common/a10soc: Bridge support 2021-02-05 10:24:59 +02:00
Istvan Csomortani f0b753321a common/intel: Add util_adcfifo integration script 2021-02-05 10:24:59 +02:00
Istvan Csomortani 3041e77659 ad40xx/zed: Update constraints 2021-02-04 11:04:32 +02:00
Istvan Csomortani 05469a011c ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA 2021-02-04 11:04:32 +02:00
Laszlo Nagy dd4c8d6807 adrv9001/zcu102: Add debug header 2021-01-26 15:22:41 +02:00
Laszlo Nagy 728904af09 adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing 2021-01-26 15:22:41 +02:00
Laszlo Nagy bae7e48c50 adrv9001/common: Run DMAs @ 100MHz 2021-01-26 15:22:41 +02:00
Sergiu Arpadi f68c222489 cn0501/coraz7s: Fix sysid 2021-01-22 15:40:37 +02:00
Laszlo Nagy bb44e5399f adrv9001/zed: Connect TDD sync to PMOD JA1 2021-01-20 13:00:01 +02:00
Laszlo Nagy 3918d43cd1 adrv9001/zcu102: Add TDD sync to PMOD0 J55.1 2021-01-20 13:00:01 +02:00
Laszlo Nagy fe9f72db9c adrv9001/common: Export TDD mode signal 2021-01-20 13:00:01 +02:00
Laszlo Nagy 18b2a8b0a7 adrv9001/zed: Add TDD support 2021-01-20 13:00:01 +02:00
Laszlo Nagy 0c2745361b adrv9001/zcu102: Add TDD support 2021-01-20 13:00:01 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
Sergiu Arpadi da61515d41 ad40xx: Fix bd.tcl script 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Laszlo Nagy da9828a63e ad9081:zcu102: Expose parameters to environment 
Allow setting project parameters from the environment.
 2021-01-19 17:10:08 +02:00