Commit Graph

14 Commits (6b15704b7008cef6316e4f2e18f6e0a91c8a221f)

Author SHA1 Message Date
Rejeesh Kutty 71b5004b25 projects- drp moved to up-clock domain 2015-06-01 14:57:59 -04:00
Lars-Peter Clausen ab5c7bb57b common: zc702: Use interface connection for the HDMI DMA stream
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Adrian Costina ea303c6f61 zc702: Updated base design to the latest model 2015-03-13 12:44:08 +02:00
Istvan Csomortani ba53e156e3 ZC702_base: Interrupt update 2014-10-30 18:39:49 +02:00
Istvan Csomortani a870603db5 common_bd: Update the common block designs to the new IRQ path
Avoid the use of xil_concat module by using the ad_interrupts.
2014-10-27 19:44:25 +02:00
Lars-Peter Clausen 7d3be14ab5 common: Connect audio clkgen reset
While we are at it also hide the unused locked pin.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
Lars-Peter Clausen fd89458708 common: Set cpu interconnect strategy to minimize area
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
Lars-Peter Clausen 43e9b0c7a6 common: Disable TTC0 MMIO routing for PS7
We do not use the ttc0 to MMIO routing, but it is enabled by default, so
explicitly disable it.
2014-10-10 16:19:51 +03:00
Adrian Costina 041d8faaf7 common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2 2014-09-30 10:31:00 +03:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Istvan Csomortani f9a67371c0 Zynq Base System: Reset is synchronized to lowest system clock
System reset (sys_100m_reset) is synchronized to lowest system
	clock (FCLK0), via a Processor System Reset module
2014-03-26 17:58:14 +02:00
Rejeesh Kutty dc44703cf1 zynq/non-zynq: identical signal names and instances 2014-03-17 17:02:03 -04:00
Rejeesh Kutty f3ae57a53e global clock and reset names 2014-03-11 09:57:59 -04:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00