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1675 Commits (6b15704b7008cef6316e4f2e18f6e0a91c8a221f)

Author SHA1 Message Date
Istvan Csomortani 19732d89fb plddr3: Fix the adc_dwr pulse width 
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
 2014-12-09 13:51:00 +02:00
Istvan Csomortani 4d28825741 ad9467_kc705: Fix typos. 2014-12-09 13:46:51 +02:00
Istvan Csomortani a0d5e7862e ad9467_kc705: Fix typos. 2014-12-09 12:07:49 +02:00
Istvan Csomortani 915ee7a268 fmcjesdadc1_kc705: Connect the SPI interrupt to the controller 2014-12-09 11:54:16 +02:00
Istvan Csomortani ee04eb637b ad9467_kc705: Fix interrupts 2014-12-09 11:54:08 +02:00
Istvan Csomortani 37c3af9929 fmcjesdadc1_kc705: Connect the SPI interrupt to the controller 2014-12-09 11:51:36 +02:00
Istvan Csomortani b83299c606 ad9467_kc705: Fix interrupts 2014-12-09 11:48:46 +02:00
Adrian Costina 6aad2fbbb2 axi_hdmi_tx: Fixed typo in altera related core 2014-12-09 10:19:03 +02:00
Adrian Costina 6f8c259961 axi_hdmi_tx: Fixed typo in altera related core 2014-12-09 09:56:14 +02:00
Rejeesh Kutty 1b4a4bc06e daq3: compilation fixes - latest changes 2014-12-08 14:51:52 -05:00
Rejeesh Kutty c0d588ba8c daq3: compilation fixes - latest changes 2014-12-08 14:51:52 -05:00
Rejeesh Kutty 26d72d306e daq3: compilation fixes - latest changes 2014-12-08 14:51:51 -05:00
Rejeesh Kutty abff7097f6 daq3: compilation fixes - latest changes 2014-12-08 14:50:03 -05:00
Rejeesh Kutty 8a72a6a0dc daq3: compilation fixes - latest changes 2014-12-08 14:49:52 -05:00
Rejeesh Kutty 7c3ed75b79 daq3: compilation fixes - latest changes 2014-12-08 14:49:40 -05:00
Rejeesh Kutty 40287f4d97 remove fmcadc3 2014-12-08 14:39:43 -05:00
Rejeesh Kutty b6b5759662 Merge branch 'hdl_2014_r2' 
Conflicts:
	library/axi_ad9234/axi_ad9234.v
	library/axi_ad9234/axi_ad9234_channel.v
	library/axi_ad9234/axi_ad9234_constr.xdc
	library/axi_ad9234/axi_ad9234_if.v
	library/axi_ad9234/axi_ad9234_ip.tcl
	library/axi_ad9234/axi_ad9234_pnmon.v
	library/axi_ad9434/axi_ad9434.v
	library/axi_ad9434/axi_ad9434_core.v
	projects/ad9434_fmc/common/ad9434_bd.tcl
	projects/ad9467_fmc/common/ad9467_bd.tcl
	projects/common/kc705/kc705_system_bd.tcl
	projects/common/kcu105/kcu105_system_bd.tcl
	projects/common/mitx045/mitx045_system_bd.tcl
	projects/common/vc707/vc707_system_bd.tcl
	projects/common/zc706/zc706_system_bd.tcl
	projects/daq1/common/daq1_bd.tcl
	projects/daq1/zc706/system_top.v
	projects/fmcomms1/ac701/system_top.v
	projects/fmcomms1/common/fmcomms1_bd.tcl
	projects/fmcomms2/ac701/system_constr.xdc
	projects/fmcomms2/common/fmcomms2_bd.tcl
	projects/fmcomms2/zc702/system_constr.xdc
	projects/usdrx1/common/usdrx1_bd.tcl
 2014-12-08 14:25:00 -05:00
Rejeesh Kutty 0a8fabe874 Merge branch 'hdl_2014_r2' into dev 
Conflicts:
	projects/fmcadc5/common/fmcadc5_bd.tcl
	projects/motcon1_fmc/common/motcon1_fmc_bd.tcl
	projects/motcon1_fmc/zed/system_constr.xdc
	projects/motcon1_fmc/zed/system_top.v
 2014-12-08 11:32:13 -05:00
Rejeesh Kutty 82b9ebe23d remove replaced projects 2014-12-08 10:45:12 -05:00
Rejeesh Kutty 19e4950b72 renamed to match official names 2014-12-08 10:44:15 -05:00
Adrian Costina a558d4000d motcon1_fmc: Added XADC to the project, the external muxing is controlled by generic GPIO, not XADC GPIO 2014-12-08 11:27:47 +02:00
Paul Cercueil d5572eaa49 ad9265_fmc: Fix unconnected DMA irq 
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
 2014-12-05 17:44:47 +01:00
Michael Hennerich 84174460bb projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-12-05 14:50:45 +01:00
Michael Hennerich bb6cc40902 projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-12-05 14:50:45 +01:00
Michael Hennerich 8e4d0a1b60 projects/common: KCU105 VC707 KC705 sync microblaze core defaults 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-12-05 14:50:45 +01:00
Michael Hennerich 7e18162632 projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-12-05 14:48:37 +01:00
Adrian Costina e6e9c0058d motor_control: Updated project to Vivado 14.2. Temporary removed XADC 
- fixed constraints
- updated interrupt system
- used ad_iobuf
- The XADC was removed because the XADC IPI generates vaux inputs 0 and 10 even if 0 and 8 are selected
 2014-12-05 11:53:23 +02:00
Adrian Costina a70d27c094 axi_mc_speed: updated core to latest axi interface implementation 2014-12-05 11:53:11 +02:00
Adrian Costina 26f58914e2 axi_mc_current_monitor: updated core to latest axi interface implementation 2014-12-05 11:53:06 +02:00
Adrian Costina 7e8e1e4fd0 axi_mc_controller: updated core to latest axi interface implementation 2014-12-05 11:52:59 +02:00
Adrian Costina 4c05e8de5d motor_control: Updated project to Vivado 14.2. Temporary removed XADC 
- fixed constraints
- updated interrupt system
- used ad_iobuf
- The XADC was removed because the XADC IPI generates vaux inputs 0 and 10 even if 0 and 8 are selected
 2014-12-05 11:48:00 +02:00
Adrian Costina ea1a50c985 axi_mc_speed: updated core to latest axi interface implementation 2014-12-05 11:46:20 +02:00
Adrian Costina 0d2888a5a6 axi_mc_current_monitor: updated core to latest axi interface implementation 2014-12-05 11:45:37 +02:00
Adrian Costina 21591dc485 axi_mc_controller: updated core to latest axi interface implementation 2014-12-05 11:43:59 +02:00
Istvan Csomortani 11f41d1dff zynq_plddr3: Fix PLDDR3's Reset Generator 
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
 2014-12-04 15:42:28 +02:00
Istvan Csomortani 34ffa15b12 zynq_plddr3: Fix PLDDR3's Reset Generator 
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
 2014-12-04 15:39:17 +02:00
Lars-Peter Clausen 58bc7c6886 fmcomms6: Add DMA overflow signal to ILA 
This is useful for debugging DMA overflows.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-12-04 14:23:09 +01:00
Lars-Peter Clausen a9c6148570 fmcomms6: Better cope with higher sample rates 
There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-12-04 13:56:59 +01:00
Lars-Peter Clausen 324c0528c2 fmcomms6: Better cope with higher sample rates 
There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-12-04 13:28:37 +01:00
Lars-Peter Clausen 46156b7ceb fmcomms6: Add DMA overflow signal to ILA 
This is useful for debugging DMA overflows.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-12-04 13:28:37 +01:00
Michael Hennerich 3cc890e604 projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-12-04 09:49:09 +01:00
Michael Hennerich 2d8450abc4 Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev 2014-12-04 09:47:46 +01:00
Michael Hennerich 3bc9b25e96 projects/common: KCU105 VC707 KC705 sync microblaze core defaults 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-12-04 09:47:02 +01:00
Istvan Csomortani 56a8a54080 ad9625x2_fmc: Increase the dma fifo data depth 2014-12-03 12:13:08 +02:00
Istvan Csomortani 757c213165 ad9625x2_fmc: Integrate the dac spi interface into the SPI interface 2014-12-03 12:06:43 +02:00
Istvan Csomortani 48673fec6a ad9625x2_fmc: Integrate the dac spi interface into the SPI interface 2014-12-03 12:01:47 +02:00
Istvan Csomortani 80d1314c5e ad9625x2_fmc: Reverse "Add a separate SPI for the DAC interface" 2014-12-03 10:14:09 +02:00
Istvan Csomortani d89ed56e10 ad9625x2_fmc: Increase the data depth of the dmafifo 2014-12-02 19:29:19 +02:00
Istvan Csomortani 0007054638 ad9625x2_fmc: Add a separate SPI for the DAC interface 
DAC spi interface is controlled by an axi_spi core.
Modifications on GPIO layout: pwr_good is 12, vdither 13 and trig is 14.
 2014-12-02 19:29:18 +02:00
Rejeesh Kutty 2e611ca013 Merge branch 'hdl_2014_r2' into dev 2014-12-02 10:45:35 -05:00