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4577 Commits (6baf7612f75ff612cc55b2e2f57b43ee3025bee3)

Author SHA1 Message Date
Istvan Csomortani f100a6bf21 avl_dacfifo: Delete deprecated false path definition 2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani 34994222b4 license: Update old license headers 2018-04-11 15:09:54 +03:00
Laszlo Nagy ee79ba5686 axi_hdmi_tx: removed unused registers 2018-04-11 15:09:54 +03:00
Istvan Csomortani 9a76bd4536 axi_adxcvr: Set the init value of the configuration registers 2018-04-11 15:09:54 +03:00
Istvan Csomortani 571b721274 util_adxcvr: CPLLPD should be used for reset 
For CPLL reset the CPLLPD ports should be used, instead of the
CPLLRESET. The recommended reset width is above 2us.
See UG576 pg. 60 for more detail.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 4e60f15e7f axi_clkgen: Add a parameter to control the clock source options 
Add a parameter to the control the clock source option of the MMCM. If
the MMCM has only one clock source the CLKSEL pin will be tied to VDD.

The previous version added a redundant path between the CLKSEL port and
register map.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani bd8c71c2ec adrv9371x:zcu102: Set DEVICE_TYPE to ultrascale 2018-04-11 15:09:54 +03:00
Istvan Csomortani d1b91c6019 fmcadc2: Delete redundant settings 
This project has only receive paths, all transmit related setting of the
transceivers are redundant.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani f565818ab2 adi_xilinx_msg: eth_avb is not used by our designs 2018-04-11 15:09:54 +03:00
Rejeesh Kutty 72431ff952 a10soc: Connect AXI register reset 2018-04-11 15:09:54 +03:00
Adrian Costina a5407702bb util_adxcvr: Don't show reset ports for disabled lanes 2018-04-11 15:09:54 +03:00
Laszlo Nagy 0d01c08b00 util_[c|u]pack_dsf: clear syntehsis warnings 
Remove unused registers and move register definitions to the generate block
that is actually using it.
 2018-04-11 15:09:54 +03:00
Laszlo Nagy bce0cf8e22 util_[w|r]fifo: Reduce synthesis warnings 2018-04-11 15:09:54 +03:00
Laszlo Nagy eedd8ed5d8 up_delay_cntrl: Fix synthesis warnings, no functional changes 
Reduce the number of synthesis warnings with the help of a generate
statement. When the block is disabled do not generate any logic.
 2018-04-11 15:09:54 +03:00
Laszlo Nagy b4ab639db5 up_[adc|dac]_common: Define the DPR registers only when the interface is enabled 2018-04-11 15:09:54 +03:00
Laszlo Nagy 5cba46165a axi_dmac: fix synthesis warnings 
Separated the 2D transfer registers to a separate generate block
 2018-04-11 15:09:54 +03:00
Adrian Costina c0184bce59 adrv9379: Fix lane assignment, according to schematic 2018-04-11 15:09:54 +03:00
Laszlo Nagy 4bcf45a17a common: clean up synthesis warnings 
Removed unused registers and define registers only when they are in use.
 2018-04-11 15:09:54 +03:00
Laszlo Nagy b6d2def504 axi_ad9361: clear synthesis warnings 
Defined the delay registers only when they are used.
 2018-04-11 15:09:54 +03:00
AndreiGrozav 6f52ddb2c7 adrv936x: Fix Ethernet 
Explicitly select MIO 52 and 53 pins to be part of MDIO port.
MIO_52_PIN (MDIO 0 Clock, Output)
MIO_53_PIN (MDIO 0 Data, Input/Output)
After the tool version change, this pins where by default connected
as MIO GPIOs.
 2018-04-11 15:09:54 +03:00
Adrian Costina 5bfc585524 axi_dmac: Added MAX_BYTES_PER_BURST and DISABLE_DEBUG_REGISTERS parameters to Intel IP 2018-04-11 15:09:54 +03:00
Adrian Costina 25ffb91dc6 axi_hdmi_tx: Updated .sdc constraints 2018-04-11 15:09:54 +03:00
Adrian Costina a0cb3af11d axi_hdmi_tx: Use abstract multiplier module supporting both Xilinx and Intel FPGAs 2018-04-11 15:09:54 +03:00
AndreiGrozav 9877862517 fmcomms2/zc702: Fix implementation timing issues 
Changed the tool strategies for synthesis and implementation.
 2018-04-11 15:09:54 +03:00
AndreiGrozav 1a9497b5b6 daq3: Add parameters for default xcvr configuration 
The default configuration should be:
  - line rate 12.33 Gbps
  - core clk 308 MHz
 2018-04-11 15:09:54 +03:00
Laszlo Nagy 7f377454a8 daq2/fmcadc4/daq3: Disable the transfer start sync on the ADC DMA 
Explicitly disable the "Transfer Start Synchronisation Support"
since the sync lines are not connected in this project.
If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected,
Vivado 2017.4.1 no longer connects them to the defaultValue defined
in the axi_dmac ip (1). Instead he uses the defaulValue field defined
in the interface definition which in case of both interfaces is 0;
 2018-04-11 15:09:54 +03:00
Istvan Csomortani d13ff8df1e axi_dmac: In SDP mode REGCEB is connected to GND 
In newer version of Vivado (e.g. 2017.4) the REGCEB pin of the block ram
macro is connected to ground. So the following false path became
redundant.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani fcbc977cd8 axi_ad7616: Add missing port to instantiation 2018-04-11 15:09:54 +03:00
Istvan Csomortani f605b428fc spi_engine:axi_spi_engine: Add missing port to instantiations 2018-04-11 15:09:54 +03:00
Istvan Csomortani 7d0b162eda axi_ad9963: Fix port dependency definition 2018-04-11 15:09:54 +03:00
Istvan Csomortani aa90d9a6e1 ad738x_zed: Fix SCLK's pin assignment 2018-04-11 15:09:54 +03:00
Istvan Csomortani 11ece90435 ad738x: Add system variables for configuration 
- In system_bd define variable $adc_resolution, $adc_num_of_channels and
$adc_sampling_rate.
  - Add support for 12 and 14 bit resolution
 2018-04-11 15:09:54 +03:00
Istvan Csomortani a7b98c397a ad_tdd_control: Fix the tdd_burst_counter implementation 2018-04-11 15:09:54 +03:00
Istvan Csomortani 53fa482837 ad7134_fmc: Initial commit 2018-04-11 15:09:54 +03:00
Istvan Csomortani cd94f2f249 util_axis_upscale: Initial commit 
This module upscale an n*sample_width data bus into a 16 or 32*n data
bus. The samples are right aligned and supports offset binary or two's
complement data format.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 269ae40f66 spi_engine: Add support for 8 SDI lines 2018-04-11 15:09:54 +03:00
Istvan Csomortani e16f45c792 util_pulse_gen: Use equal-to for counter reset 2018-04-11 15:09:54 +03:00
Adrian Costina 017dcaed82 up_[adc|dac]_common: DRP_DISABLE should be boolean 2018-04-11 15:09:54 +03:00
Adrian Costina d3bfb33871 constraints: up_xfer_cntrl and up_xfer_status have its own constraints 
The up_xfer_cntrl and up_xfer_status modules have its own constraints files
in library/xilinx/common. Each IP which has an instance of these
modules, have to use these constraints files.

The following IPs were modified:
  - axi_adc_decimate
  - axi_adc_trigger
  - axi_dac_interpolate
  - axi_logic_analyzer
 2018-04-11 15:09:54 +03:00
Adrian Costina c81254200f ad6676evb: Fix RX_DFE_LPM_CFG parameter, as the design is used in DFE mode 
The parameter RX_DFE_LPM_CFG should be 0x954 for DFE and 0x904 in LPM
I've removed also QPLL_FBDIV parameter, as QPLL is not used in this design
 2018-04-11 15:09:54 +03:00
Adrian Costina 9c8d4b9bdf fmcadc5: Fix RXCDR_CFG parameter 
The default linux configuration is at lane rates under 6.6G and in LPM mode
 2018-04-11 15:09:54 +03:00
Adrian Costina 62fcaa7836 fmcadc5: Remove xcvr configuration options that don't matter 2018-04-11 15:09:54 +03:00
Laszlo Nagy ae02773480 axi_dacfifo: Rewrote constraints to be more specific 
Some of the wildcards matched too many paths and disabled the timing
checks on intraclock paths.
 2018-04-11 15:09:54 +03:00
Adrian Costina 98b58562d6 system_top: Non functional changes in system_tops to reduce warnings 
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.

The following system_top modules were changed:
  - ad738x_fmc
  - ad7616_sdz
  - ad77681evb
  - ad77681evb
  - ad7768evb
  - ad9739a_fmc
  - ad9434
  - adrv9739
  - fmcadc5
  - ad6676evb
  - ad9265
  - ad5766
  - fmcomms5
  - m2k
 2018-04-11 15:09:54 +03:00
Adrian Costina b2d63bf9e0 axi_ad9434: Make adc_enable controllable from the channel register map 2018-04-11 15:09:54 +03:00
Adrian Costina 493fc1d48b axi_*: Fix instantiation of up_[adc|dac]_[common|channel] 
A couple of new parameters and new ports are missing in several
up_[adc|dac]_[common|channel] instance, and generates warnings. The rule of
thumb is to use full instantiations, defining all the existing parameter and
ports of the module.

Fix all the instantiation of up_[adc|dac]_[common|channel], by defining all its
parameters and ports.
 2018-04-11 15:09:54 +03:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP 
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 3b34e8b594 up_clock_com: Fix the false path definitions for CDCs 2018-04-11 15:09:54 +03:00
AndreiGrozav 502989c25f jesd_rst_gen:constraints: Remove invalid false path definitions 
The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
 2018-04-11 15:09:54 +03:00