Commit Graph

2925 Commits (6d19041b21f98161010ea12978fc7ed12be83e28)

Author SHA1 Message Date
Istvan Csomortani 6d19041b21 dac_fmc_ebz: QPRO is using apply_instance_preset 2020-08-11 10:14:18 +03:00
Istvan Csomortani 0de5039b96 avl_dacfifo: add_intance command must have a version attribute 2020-08-11 10:14:18 +03:00
Istvan Csomortani 8fd1ad64d6 quartus: Increase tool version to 19.2 2020-08-11 10:14:18 +03:00
Istvan Csomortani f3142a6a7a adi_project_intel: set_interconnect_requirment command is deprecated
Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
2020-08-11 10:14:18 +03:00
Istvan Csomortani a39fa831d0 ad9371:a10gx: Relax interconnect requirements 2020-08-11 10:14:18 +03:00
Istvan Csomortani 7e22f91429 adrv9371:a10gx: Remove constraint from DDR 2020-08-11 10:14:18 +03:00
Istvan Csomortani 359e5d94ec a10gx: Remove constraint from eth_ref_clk 2020-08-11 10:14:18 +03:00
Istvan Csomortani 967a138d0f adi_project_intel: Add support for Quartus Pro
By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )

Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
2020-08-11 10:14:18 +03:00
Istvan Csomortani 054193e083 adi_project_intel: Delete all MESSAGE_DISABLE assignment
These kind of assignments should be placed into file like
~/projects/scripts/adi_xilinx_msg.tcl
2020-08-11 10:14:18 +03:00
Istvan Csomortani 4ca1311d57 quartus_pro: Global assignment ENABLE_ADVANCED_IO_TIMING is not supported 2020-08-11 10:14:18 +03:00
AndreiGrozav 8d6b8fc631 Add cn0506_rmii/zcu102 support on revB 2020-08-10 18:32:44 +03:00
AndreiGrozav 7e96514230 Add cn0506_rmii/zc706 support on revB 2020-08-10 18:32:44 +03:00
AndreiGrozav 321b82398b Add cn0506_rmii/zed support on revB 2020-08-10 18:32:44 +03:00
Istvan Csomortani 6c2b1b1634 fmcomms5/zc702: Fix the sys_dma_clk connections 2020-06-19 12:53:18 +03:00
Istvan Csomortani 137c31db1d daq2/xilinx: Update project to use generic JESD204 TPL 2020-06-18 15:45:19 +03:00
Istvan Csomortani 299273f5a1 daq2/intel: Update project to use generic JESD204B TPL 2020-06-18 15:45:19 +03:00
Stanca Pop 847f0f22e6 cn0540: Fix typo 2020-06-04 18:38:14 +03:00
Stanca Pop 193fce338d cn0540: Initial commit 2020-05-28 18:49:35 +03:00
Stanca Pop 03ab28d7bf ad77681evb: Remove coraz7s project 2020-05-28 18:49:35 +03:00
Istvan Csomortani 71d500bdd4 adrv9009/intel: Use generic TPL cores 2020-05-26 16:22:30 +03:00
Laszlo Nagy 9c8190f709 adi_project_xilinx.tcl: discover all timing failures
Look for an overall indicator of timing failure.
Create critical warning if timing is failed.
2020-05-26 14:47:38 +03:00
Istvan Csomortani 47a97aac7c adrv9371x/intel: Update project to use generic JESD204B TPL 2020-05-25 11:55:40 +03:00
Laszlo Nagy e8f6523197 ad9081_fmca_ebz: adapt to renamed tpl core 2020-05-20 19:08:25 +03:00
Laszlo Nagy db6af63583 scripts/adi_env.tcl: print in logs system variables are used 2020-05-20 19:07:23 +03:00
Istvan Csomortani e7600eb552 ad7616_sdz: Fix the project, after SDI ports were merged
Update the project to support the SDI port merge patch: 4d54c7e
2020-05-20 11:44:22 +03:00
Istvan Csomortani 4d54c7e2d6 spi_engine_execution: Merge the SDI lines into one vector
This modification will help to support multiple SPI engine
execution setups (e.g. different NUM_OF_SDI) for the same project.
2020-05-19 09:28:02 +03:00
Istvan Csomortani 6535e5b2ba scripts/xilinx: Version mismatch is upgraded to ERROR
There is a major compatibility issue between 2019.1 and 2019.2.

The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.

If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
2020-05-15 12:16:35 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Laszlo Nagy cbb23c7b67 ad9081_fmca_ebz: fix Xilinx PHY resets
Avoid clock domain crossing on resets.
2020-04-23 17:21:05 +03:00
Laszlo Nagy e112a03d85 ad9081_fmca_ebz: Whitespace cleanup
Clear extra lines and whitespaces at end of lines.
2020-04-23 17:21:05 +03:00
Laszlo Nagy 7df4caf8b0 ad9081_fmca_ebz: Added parameter description
Add parameter description to project and common block design file
2020-04-23 17:21:05 +03:00
Laszlo Nagy e433d3f808 ad9081_fmca_ebz: expose PLL selection as a parameter
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
  0 - CPLL
  1 - QPLL0
  2 - QPLL1

Since the selection of line rate is available from the project also the
PLL selection must be exposed.
2020-04-23 17:21:05 +03:00
Laszlo Nagy b774e1ca7d ad9081_fmca_ebz: enable IQ rotation 2020-04-03 11:16:37 +03:00
Istvan Csomortani 4684dc03ce dac_fmc_ebz/a10soc: Use balanced optimization mode
Always a good idea to start from default, and change optimization mode
of the tool if it's strict necessary.
2020-03-17 17:25:02 +00:00
Istvan Csomortani 253a8cb6ee dac_fmc_ebz/a10soc: Tool expect that all config parameters exists on top entity 2020-03-17 17:25:02 +00:00
Istvan Csomortani 522aacf6d8 ad_fmclidar1_ebz/a10soc: Fix AFE's I2C interface
The AFE's I2C interface should be pin-multiplexed to the FPGA. Also, add
a bidirectional IO buffer for the interface, and make sure it has weak
pull-up resistors.
2020-03-17 07:27:49 +00:00
Adrian Costina 19b7986486 fmcomms8: Fix SPI timing
The maximum SPI rate set to 10MHz
2020-03-16 13:26:20 +02:00
Istvan Csomortani fde79a2272 ad_fmclidar1_ebz: Fix AFE's SPI polarity 2020-03-10 16:37:18 +00:00
Laszlo Nagy b1f62f09ac ad9081_fmca_ebz:vcu118: initial version
Use over-writable parameters from the environment.

      e.g.
        make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
        make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
        make JESD_MODE=8B10B  RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2020-03-10 18:19:03 +02:00
Laszlo Nagy f3a7fd8b0d ad9081_fmca_ebz:zcu102: initial version 2020-03-10 18:19:03 +02:00
Laszlo Nagy f3630dd95b ad9081_fmca_ebz: common block design
Parametrizable block design with selectable JESD physical layer between
Xilinx Phy and ad_utilxcvr.
2020-03-10 18:19:03 +02:00
Laszlo Nagy 1f7671cb36 scripts/adi_env.tcl: helper function for environment variables
Ease the access of the environment variables.
2020-03-10 18:19:03 +02:00
Adrian Costina fad52175d1 fmcomms8: Fix spi connection 2020-03-06 16:07:02 +02:00
Adrian Costina 50d904934a fmcomms8: Changed the interrupt addresses to be similar with adrv9009zu11eg project 2020-03-06 16:07:02 +02:00
AndreiGrozav e1353d5291 m2k: use DMA streaming interface
The previous mechanism was "probing" the DMAs for valid data. Better said,
each interpolation channel enabled it's DMA until a valid data was received,
then it disabled the DMA read and waited for the adjacent channel(DMA) to
receive a valid data. Only when for both channels had valid data on the
DMAs interfaces was the transmission started. This added an undesired and
redundant complexity to the interpolation channels. Furthermore, for continuous
transmission, using the above mechanism lead to a fixed phase(sample)
shift between the two channels at each start.

By using the streaming mechanism the interface is simplified and the
above problems are solved.
2020-03-06 15:57:43 +02:00
sarpadi dd47e30431 ad7768_evb_sync: Fixed sync issue
fixed sync inside ad7768_if module;
2020-03-04 18:21:55 +02:00
Laszlo Nagy 35412c81a9 dac_fmc_ebz: drive spi_en pin automatically based on FMC board selected
spi_en is active ...
   ... high for AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ,
   ... low for AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
2020-03-03 15:49:30 +02:00
Laszlo Nagy ef15757d9e common:vcu118: support for plddr4 adc and dac fifo
Use 1GB from the DDR4 for either ADC or DAC sample buffering.
Max theoretical bandwidth of 19.2 GB/s
2020-03-03 15:49:11 +02:00
StancaPop 48a91796e2
ad77681evb: Set spi_clk to 40MHz (#435) 2020-02-24 12:55:06 +02:00
Laszlo Nagy 37188b01d8 fmcomms2:a10soc: use non DPA mode 2020-02-24 11:31:01 +02:00