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9 Commits (6d19041b21f98161010ea12978fc7ed12be83e28)

Author SHA1 Message Date
Laszlo Nagy e8f6523197 ad9081_fmca_ebz: adapt to renamed tpl core 2020-05-20 19:08:25 +03:00
Laszlo Nagy cbb23c7b67 ad9081_fmca_ebz: fix Xilinx PHY resets 
Avoid clock domain crossing on resets.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy e112a03d85 ad9081_fmca_ebz: Whitespace cleanup 
Clear extra lines and whitespaces at end of lines.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy 7df4caf8b0 ad9081_fmca_ebz: Added parameter description 
Add parameter description to project and common block design file
 2020-04-23 17:21:05 +03:00
Laszlo Nagy e433d3f808 ad9081_fmca_ebz: expose PLL selection as a parameter 
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
  0 - CPLL
  1 - QPLL0
  2 - QPLL1

Since the selection of line rate is available from the project also the
PLL selection must be exposed.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy b774e1ca7d ad9081_fmca_ebz: enable IQ rotation 2020-04-03 11:16:37 +03:00
Laszlo Nagy b1f62f09ac ad9081_fmca_ebz:vcu118: initial version 
Use over-writable parameters from the environment.

      e.g.
        make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
        make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
        make JESD_MODE=8B10B  RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
 2020-03-10 18:19:03 +02:00
Laszlo Nagy f3a7fd8b0d ad9081_fmca_ebz:zcu102: initial version 2020-03-10 18:19:03 +02:00
Laszlo Nagy f3630dd95b ad9081_fmca_ebz: common block design 
Parametrizable block design with selectable JESD physical layer between
Xilinx Phy and ad_utilxcvr.
 2020-03-10 18:19:03 +02:00