f2ca956d23
pluto: Fix dunf connection
2021-08-05 18:08:12 +03:00
bbb151f9f5
adi_project_xilinx.tcl: Set default value of ADI_USE_OOC_SYNTHESIS to 1
...
In order to workaround optimization issues hit in Vivado 2020.2,
set ADI_USE_OOC_SYTHESIS variable by default to 1. This will build
projects in Out Of Context mode.
Projects can be build in Project Mode by exporting ADI_USE_OOC_SYTHESIS=n.
2021-07-29 14:06:42 +03:00
9d5de2fc21
Update Vivado version to 2020.2
...
Update vivado version to 2020.2:
- update default vivado version from 2020.1 to 2020.2
- add conditions to apply specific contraints only in Out Of Context mode.
- update DDR controler parameters for vcu118 and kcu105 dev boards
2021-07-29 14:06:42 +03:00
907b750943
ad9083: Removed FIFO and increased DMAC transfer length
2021-07-28 12:45:20 +03:00
8343c03f5c
adrv9371x: remove IOB attribute from rx and rx_os
2021-07-26 12:42:21 +01:00
1158538753
adi_board: Fix ad_connect command tracing
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-07-22 15:02:36 +03:00
796af696da
ad_fmclidar1_ebz: Remove invalid ad_connect invocations
...
This commit removes two invalid ad_connect invocations, which weren't
caught in the original tests for commit cdda184007
2021-07-22 15:02:25 +03:00
a3e049ae03
scripts/adi_project_xilinx: Set number of parallel OOC jobs through environment variable
2021-07-13 10:09:08 +03:00
cdda184007
adi_board: Rewrite ad_connect to support all input permutations
...
The goal of this commit is to make sure there isn't any significance to
the order in which parameters of ad_connect are specified.
As an example, previously you could only `ad_connect target VCC`, while
`ad_connect VCC target` would fail.
Note: This code intentionally ignores bd_{,intf_}ports, because
these can all be treated as bd_pins.
Signed-off-by: David Winter <david.winter@analog.com>
2021-07-09 12:43:31 +03:00
63ac142874
adrv9001:a10soc:system_qsys.tcl: set clock polarity to 0
...
For fixing "Failed to reset the device and set SPI Config"
error, both clockPolarity and clockPhase should be disabled
or both enabled. By default both are unset.
Signed-off-by: Stefan Raus <stefan.raus@analog.com>
2021-06-16 11:42:50 +03:00
75b965e87f
ad9081_fmca_ebz/zcu102: Enable 204C modes
2021-06-10 09:53:43 +03:00
6637436c2e
scripts/adi_board.tcl: Use div2 out clock from xcvr in case of GTH and 204C
2021-06-10 09:53:43 +03:00
27465ce9c0
ad9081_fmca_ebz/zcu102: Fix spaces
2021-06-10 09:53:43 +03:00
7b7609d21a
ad469x: Clean system_project.tcl
2021-06-03 15:41:58 +03:00
d9bc014c98
adrv9001/zcu102: Enable independent Tx from Rx in CMOS mode
2021-05-26 15:44:45 +03:00
568bef4a38
adrv9001/a10soc: Initial version
...
This project supports CMOS mode only.
2021-05-26 15:44:45 +03:00
5d008c3eca
Correct constraints file pin mapping
2021-05-25 16:27:58 +03:00
0ad691a603
ad9081_fmca_ebz/zcu102: Differentiate parameters based on lane rate
2021-05-14 15:39:40 +03:00
8183599b51
ad9081_fmca_ebz/zcu102: Fix typo
2021-05-14 15:39:40 +03:00
cf7f45ffcc
ad9081_fmca_ebz: Fix for F=8
2021-05-14 15:39:40 +03:00
7b2ba41bdd
ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing
...
This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
2021-05-14 15:39:40 +03:00
eba3409d78
ad9082_fmca_ebz: Use 9081 system_bd, updated comments
2021-05-14 15:39:40 +03:00
0d9e38bdbe
ad9081_fmca_ebz: Update path to common block design
...
Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
2021-05-14 15:39:40 +03:00
680d28476c
ad9081_fmca_ebz: Add LANE_RATE param to all projects
...
The block design expects a lane rate to be set in the system project.
2021-05-14 15:39:40 +03:00
bd6ec360e2
ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link
...
Set XCVR parameter for 204C 24.75 Gbps with a dynamic range of 10Gbps..24.75Gpbs
Organize XCVR params based on lane rate
2021-05-14 15:39:40 +03:00
693c002668
ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR
...
Remove Xilinx PHY and simplify project
2021-05-14 15:39:40 +03:00
d92f925b06
ad9081_fmca_ebz: Disable XBAR from DAC TPL
2021-05-14 15:39:40 +03:00
77a5edaa83
scripts/adi_board.tcl: In 204C do not connect SYNC
...
Take link mode parameter from util_adxcvr, check it against the axi_adxcvr.
2021-05-14 15:39:40 +03:00
1db04a47b8
ad9083_evb: Update parameters to 10Gpbs lane rate
2021-04-19 13:21:34 +03:00
8335e1bd9a
sysid: Make sure gitbranch_string is always declared
...
Parsing of not existed "gitbranch_string" fails the build process.
2021-03-24 13:34:32 +02:00
6a374ef457
ad469x/zed: Add multicycle path constraint
2021-03-22 13:05:05 +02:00
40baa63f0f
adrv2crr_fmcomms8: Fix system_top.v
2021-03-19 17:56:28 +02:00
a1773c661c
adrv9009zu11eg_crr: Update spi
...
Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
3dce87d09b
ad9083: Add reference design for ad9083 eval board
2021-03-10 10:52:03 +02:00
dcec4fe1b7
adrv9001/zc706: Fix spaces
2021-03-10 10:35:52 +02:00
dc186645d8
adrv9001/zc706: Fix comments HPC to LPC
2021-03-10 10:35:52 +02:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
...
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
1099badaf4
ad9082_fmca_ebz:zc706: Initial version
2021-03-05 15:54:23 +02:00
2213527f29
ad9082_fmca_ebz:zcu102: Initial version
2021-03-05 15:54:23 +02:00
f56e3c305b
ad9082_fmca_ebz:vcu118: Initial version
2021-03-05 15:54:23 +02:00
6b13b32f24
ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
2021-03-04 11:13:29 +02:00
677c154134
adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
...
Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
2021-03-04 11:13:10 +02:00
03de08609b
fmcomms2/zed: Disable unused TDD to save space and timing
2021-03-04 11:13:10 +02:00
0dd3173547
adrv9001/zc706: Initial commit
...
The project supports CMOS interface only.
VADJ on the ZC706 must be programmed to 1.8V
Instructions can be found here:
https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086
2021-03-03 09:03:03 +02:00
3be5137aec
cn0540/cora: Remove multicycle constraint
...
Design uses 80MHz spi_clk which does not require
special considerations
2021-02-18 14:14:16 +02:00
701e5f6515
scripts/adi_board.tcl: Add simulation support
...
This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
2021-02-12 16:21:10 +02:00
0374a7c1ac
ad9081_fmca_ebz/vcu118: Added common 204C use cases as example
2021-02-05 15:24:15 +02:00
ddd8a14790
ad9081_fmca_ebz: Remove system reset from Xilinx PHY
...
Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
2021-02-05 15:24:15 +02:00
af3e1c7003
ad9081_fmca_ebz/a10soc: Np 12 support
2021-02-05 15:24:15 +02:00
f73ed741c9
fmcadc5: Connect link clock to second JESD link layer
2021-02-05 15:24:15 +02:00
Adrian Costina
stefan.raus
Iacob_Liviu
David Winter
Laszlo Nagy
sergiu arpadi
Owen McAree
vladimirnesterov