Istvan Csomortani
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1d4b92190a
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fmcomms2/zc702: Fix Warning[Synth 8-2611]
In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
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2017-04-19 13:54:03 +03:00 |
Adrian Costina
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942d69a30c
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Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
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2017-04-18 10:57:16 +03:00 |
|
Istvan Csomortani
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1c23cf4621
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all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
Rejeesh Kutty
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7e87ecae22
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altera/a10gx- daq1/fmcomms2 fix typos
|
2017-03-22 09:48:02 -04:00 |
|
Rejeesh Kutty
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8063ba2b66
|
make updates
|
2017-03-20 16:05:18 -04:00 |
|
Rejeesh Kutty
|
9b6dd27c23
|
ad9361- delay initialization
|
2017-03-15 12:06:59 -04:00 |
|
Rejeesh Kutty
|
c3c8c366d3
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axi_ad9361- add receive init delay
|
2017-03-13 16:28:53 -04:00 |
|
Rejeesh Kutty
|
0ae79ca7ac
|
move/rename - delay script belongs to ad9361
|
2017-03-10 12:44:32 -05:00 |
|
Rejeesh Kutty
|
452e5e5ce0
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fmcomms2- add delay reporting for iodelay
|
2017-03-09 15:29:15 -05:00 |
|
Rejeesh Kutty
|
8bdfbe2b0a
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fmcomms2- report delays
|
2017-03-09 15:21:42 -05:00 |
|
Rejeesh Kutty
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c598e84258
|
remove processing order (no clock def dependency)
|
2017-02-22 16:02:08 -05:00 |
|
Rejeesh Kutty
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8a5e2ff46e
|
sys_wfifo- removed
|
2017-02-22 15:13:18 -05:00 |
|
Rejeesh Kutty
|
58872aa3ef
|
fmcomms2/zc706pr- prcfg is a single clock synchronous design
|
2017-02-06 10:59:18 -05:00 |
|
rejeesh kutty
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48ad24cdbe
|
enable partial reconfiguration mode
|
2017-01-27 09:26:53 -05:00 |
|
Adrian Costina
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4dcad7e116
|
fmcomms2: zcu102, update clkdiv device parameter
|
2017-01-16 14:38:37 +02:00 |
|
Adrian Costina
|
a36057679a
|
fmcomms2: Update Makefiles
|
2017-01-13 14:16:21 +02:00 |
|
Adrian Costina
|
15c5bc7012
|
fmcomms2: zcu102, changed clkdiv C_SIM_DEVICE parameter to ultrascale
|
2017-01-13 13:57:32 +02:00 |
|
Adrian Costina
|
b84325d43f
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fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection
|
2017-01-13 13:56:04 +02:00 |
|
Adrian Costina
|
e77428c50e
|
fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4
- removed ILA
|
2017-01-11 18:12:35 +02:00 |
|
Rejeesh Kutty
|
4a783d523d
|
projects/altera* - default & common qsys commands
|
2016-12-20 16:27:44 -05:00 |
|
Adrian Costina
|
8ebc8fe4e2
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
AndreiGrozav
|
b0eff57b0f
|
fmcomms2/zc702: Fix critical warnings
|
2016-12-08 19:54:52 +02:00 |
|
Rejeesh Kutty
|
170c781d02
|
hdlmake.pl- updates
|
2016-12-01 13:52:11 -05:00 |
|
Rejeesh Kutty
|
69ee410d3d
|
fmcomms2/zc706pr- bypass pr as default
|
2016-11-21 09:45:10 -05:00 |
|
Rejeesh Kutty
|
1cbea90bac
|
altera - a10gx bank swap
|
2016-11-01 12:41:25 -04:00 |
|
Rejeesh Kutty
|
1e0fed82f7
|
alt_serdes- a10 ddio fixes
|
2016-11-01 12:41:25 -04:00 |
|
Rejeesh Kutty
|
671a547c2b
|
hdlmake- updates
|
2016-11-01 12:41:25 -04:00 |
|
Rejeesh Kutty
|
7b958fed87
|
hdlmake- updates
|
2016-10-21 13:59:43 -04:00 |
|
AndreiGrozav
|
17cfdd6be9
|
fmcomms2/a10gx: Update Makefile and qsys script
|
2016-10-18 12:42:14 +03:00 |
|
Rejeesh Kutty
|
cb97bc500a
|
hdlmake updates
|
2016-10-17 16:29:57 -04:00 |
|
Rejeesh Kutty
|
905e29eb01
|
hdlmake- altera
|
2016-10-10 12:55:55 -04:00 |
|
Rejeesh Kutty
|
8e1034946f
|
fmcomms2/zcu102- 2016.2 updates
|
2016-09-30 11:55:10 -04:00 |
|
Istvan Csomortani
|
f1e787f86b
|
fmcomms2: TDD control is enabled by default
|
2016-09-16 14:45:39 +03:00 |
|
Istvan Csomortani
|
16ee1336c3
|
Makefile: Update make files
|
2016-09-15 11:41:06 +03:00 |
|
Rejeesh Kutty
|
f697490de6
|
hdlmake- updates
|
2016-08-19 15:59:41 -04:00 |
|
Adrian Costina
|
0b0aa8e6c0
|
Makefile: Add MMU option to altera makefiles
|
2016-08-11 17:46:54 +03:00 |
|
Istvan Csomortani
|
0cd608a7e2
|
lib_refactoring: Update Make files
|
2016-08-08 16:38:38 +03:00 |
|
Istvan Csomortani
|
df36902713
|
lib_refactoring: Fix path of the IO macros
|
2016-08-08 15:07:19 +03:00 |
|
Adrian Costina
|
d60bce654c
|
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
|
2016-08-05 15:16:04 +03:00 |
|
Rejeesh Kutty
|
e42b4ea378
|
hdlmake- updates
|
2016-08-04 13:28:25 -04:00 |
|
Istvan Csomortani
|
7ca8e10004
|
make: Update Make files
|
2016-08-01 14:24:48 +03:00 |
|
Istvan Csomortani
|
af4c43b6e1
|
hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design
|
2016-08-01 13:49:12 +03:00 |
|
Rejeesh Kutty
|
39a5534e00
|
hdlmake- updates
|
2016-07-21 16:10:38 -04:00 |
|
AndreiGrozav
|
12abe2b6b9
|
fmcomms2: Makefile update
|
2016-07-12 09:39:24 +03:00 |
|
AndreiGrozav
|
283bf9ad75
|
fmcomms2_a10GX: Add fmcomms2 on a10gx
|
2016-07-11 18:37:18 +03:00 |
|
AndreiGrozav
|
e9fe752b7a
|
fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera
|
2016-07-11 18:34:21 +03:00 |
|
Rejeesh Kutty
|
48762519b5
|
make updates
|
2016-07-06 15:02:00 -04:00 |
|
Rejeesh Kutty
|
67c948e821
|
fmcomms2/a10soc-- bad board design
|
2016-06-14 12:29:36 -04:00 |
|
Rejeesh Kutty
|
eaf4d4a19d
|
makefile updates
|
2016-06-10 14:26:14 -04:00 |
|
Rejeesh Kutty
|
09520709b0
|
make updates
|
2016-05-20 12:35:45 -04:00 |