Commit Graph

2 Commits (6f4235a11b53dafae68b4f18f80c2f138e2938f4)

Author SHA1 Message Date
Jorge Marques 8e32f0e21d
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 10:05:12 -03:00
LBFFilho 0f87d845d3
SPI Engine: Add execution delay documentation (#1230)
* SPI Engine: Add execution delay documentation

Add documentation for the different delays on the command path and
data path, including communication between submodules and instruction
execution overhead.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2023-11-28 18:08:51 -03:00