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352 Commits (70cc53bbc8fd73ba872f88b51159e552b3a0c3ef)

Author SHA1 Message Date
LIacob106 d4126739b4 projects: remove hardcoded div_clk from xcvr 2021-10-27 12:11:22 +03:00
Mihaita Nagy ff090b60ef daq2/zcu102: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 3640c2b584 daq2/kcu105: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 6ad54c1056 daq2/kc705: Fix the ad9144 data offload to use internal bram 2021-10-15 15:03:22 +03:00
Mihaita Nagy 907cd613aa daq2/zc706: Increase BRAM utilization to 52% 2021-10-15 15:03:22 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Mihaita Nagy b354d517f5 daq2: Connected loose ad9144 dunf flag that fixes the critical warning 2021-08-20 10:38:52 +03:00
Istvan Csomortani 4026f2d414 daq2/zc706: PL DDR size is 1GByte 2021-08-06 11:55:24 +03:00
Istvan Csomortani dc910420bd daq2: Integrate data_offload 2021-08-06 11:55:24 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Istvan Csomortani 9cac38017b daq2/a10soc: Set optimization mode to high performance effort 2020-09-25 12:56:14 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Istvan Csomortani 8818089015 a10soc: Reconfiguration interface address width improvement 
The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
 2020-09-09 14:15:37 +03:00
Istvan Csomortani b54effc9c9 daq2/a10gx: Set optimization mode to aggressive performance 2020-08-17 10:43:03 +03:00
Istvan Csomortani 02ada3bbf7 a10gx: Delete input/output delay definitions 
All input and output delays should be referenced to a virtual clock.

If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
 2020-08-11 10:14:18 +03:00
Istvan Csomortani 1c907b9248 daq2/a10gx: Use the default optimization mode 2020-08-11 10:14:18 +03:00
Istvan Csomortani f3142a6a7a adi_project_intel: set_interconnect_requirment command is deprecated 
Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
 2020-08-11 10:14:18 +03:00
Istvan Csomortani 137c31db1d daq2/xilinx: Update project to use generic JESD204 TPL 2020-06-18 15:45:19 +03:00
Istvan Csomortani 299273f5a1 daq2/intel: Update project to use generic JESD204B TPL 2020-06-18 15:45:19 +03:00
Laszlo Nagy e22016de4c adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters 
Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
 2019-10-08 10:38:46 +03:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Adrian Costina 6655829bc7 daq2: VC707: Remove project 2019-07-22 13:25:46 +01:00
Istvan Csomortani 04ce10a570 cosmetics: Change Altera to Intel in comments 2019-06-29 06:53:51 +03:00
Istvan Csomortani 6e6f1347d7 project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani ec67a381e4 adi_project: Rename the process adi_project_altera to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Laszlo Nagy 089cd882bc daq2:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy 7f16f823ff Revert "axi_dmac: add tlast to the axis interface for Intel" 
This reverts commit e2c75c015f.
 2019-05-16 13:27:19 +03:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters 
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
 2019-03-30 11:26:11 +02:00
Laszlo Nagy 9b048f1a0e daq2: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy d8e11cfce5 daq2/3: update DAC TPL base addresses 
The TPL for DACs can be relocated to addresses which match the software
expectations.
 2018-12-04 14:02:22 +02:00
Lars-Peter Clausen b9958cac00 daq2: Use new pack/unpack infrastructure 
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-11-28 11:33:11 +02:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines 
Create loopback on unused GPIO lines since Linux may rely on it.
 2018-10-04 14:19:37 +03:00
AndreiGrozav b0b149244b daq2_kcu105: Change implementation strategy 
Use Performance_Retiming strategy to meet timing.
 2018-09-27 11:45:52 +03:00
AndreiGrozav 97b1d3a21e common/daq2: Fix typo 2018-08-23 15:13:58 +03:00
AndreiGrozav 87b099d498 daq2/common: Add default util_adxcvr parameters 2018-08-21 17:12:31 +03:00
Istvan Csomortani 2293374307 adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs 
The affected projects are:
  - FMCADC2/VC707 - 16Mb
  - FMCADC5/VC707 - 16Mb
  - DAQ2/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ2/KC705  - ADC@4Mb and DAC@4Mb
  - DAQ2/VC707  - ADC@8Mb and DAC@8Mb
  - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
  - DAQ3/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
  - ADRV9371x/KCU105 - DAC@8Mb
  - ADRV9371x/ZCU102 - DAC@16Mb
 2018-08-21 11:44:05 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero 
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
 2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface 
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
 2018-08-10 17:00:11 +03:00