LIacob106
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d4126739b4
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projects: remove hardcoded div_clk from xcvr
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2021-10-27 12:11:22 +03:00 |
Adrian Costina
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591a23156b
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Makefiles: Update header with the appropriate license
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2021-09-16 16:50:53 +03:00 |
Sergiu Arpadi
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6f2f2b8626
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makefile: Regenerate make files
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2021-01-20 01:02:56 +02:00 |
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sergiu arpadi
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acbbd4636a
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sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
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2021-01-20 01:02:56 +02:00 |
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Adrian Costina
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9093a8c428
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library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
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2020-11-02 16:13:35 +02:00 |
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Sergiu Arpadi
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d8ab27b2af
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sysid: Remove cstring init string
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2020-09-30 19:12:24 +03:00 |
Istvan Csomortani
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aa5fdf903e
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Makefile: Update makefiles
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2019-08-26 16:58:01 +03:00 |
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Arpadi
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0680e44330
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system_id: deployed ip
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2019-08-06 16:53:11 +03:00 |
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Istvan Csomortani
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a589753d92
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project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
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2019-06-29 06:53:51 +03:00 |
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Istvan Csomortani
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43725429ac
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adi_project: Rename the process adi_project_xilinx to adi_project
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2019-06-29 06:53:51 +03:00 |
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Istvan Csomortani
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f22f448d4b
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daq3:vcu118: Delete constraint related to smart connect
Apparently this constraint will cause more harm than good. The tool will
try to prevent an invalid hold violation by increasing the net delay,
causing a setup violation on the same path. (inside the smart connect)
See more info here:
https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824
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2019-06-27 13:47:24 +03:00 |
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Adrian Costina
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f5ed5def27
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daq3: vcu118 initial commit
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2019-04-17 14:24:35 +03:00 |