Commit Graph

2796 Commits (7112fbce7ea65416b49d7519a1f7736883b97bfd)

Author SHA1 Message Date
Laszlo Nagy 7112fbce7e library/scripts/adi_xilinx_device_info_enc.tcl: Add K26 support 2021-11-08 09:23:02 +02:00
Nicola Corna 5d7f4672f5 axi_i2s_adi: initialize cdc_sync_stage0_tick bits to '0' 2021-11-08 08:52:01 +02:00
Nicola Corna 18ab43b5a1 axi_hdmi_tx: Add UltraScale+ architecture to Verilog 2021-11-08 08:52:01 +02:00
Dan Hotoleanu a381fe3e92 ad_ip_jesd204_tpl_adc: Add value of 14 to CONVERTER_RESOLUTION parameter
Added new allowed value of 14 for the CONVERTER_RESOLUTION parameter.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-04 12:18:06 +02:00
stefan.raus 3c07861ee8 generate_xml.sh: Replace < and > in error message
Replace < with &lt; and > with &gt; in ERRS to not broke created xml.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-03 15:22:45 +02:00
Laszlo Nagy 70cc53bbc8 ad_ip_jesd204_tpl_dac: Move external dac sync bit 2021-10-27 18:36:47 +03:00
Laszlo Nagy 7b0922e4dc library/common/up_adc_common.v: Remove tabs 2021-10-27 18:36:47 +03:00
Laszlo Nagy a9c9636780 library/common/up_dac_common.v: Cleanup spaces 2021-10-27 18:36:47 +03:00
Filip Gherman 9b7c2852b6 adxcvr: Increase version to 17.5.a
Add suport for XCVR phase adjust buffer status:
   - Expose TXBUFSTATUS and RXBUFSTATUS
   - Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
2021-10-27 14:40:50 +03:00
Laszlo Nagy d493b724f2 axi_adrv9001/adrv9001_rx.v: Simplify clocking 2021-10-27 14:40:08 +03:00
David Winter 6a5d2f76d5 data_offload: Fix oversized TX input transactions
Signed-off-by: David Winter <david.winter@analog.com>
2021-10-27 14:26:22 +03:00
David Winter cd6024b341 Revert "data_offload: Fix oversized inputs in TX mode"
This reverts commit 0e8f55b2d7.
2021-10-27 14:26:22 +03:00
sergiu arpadi 52df3c4937 ad463x_data_capture: Remove tb 2021-10-26 15:58:54 +03:00
LIacob106 076e81a17c library: Add link to wiki for IPs 2021-10-25 10:44:53 +03:00
Istvan Csomortani 6a526f4bb6 ad463x_data_capture: Initial commit
IP required to support echo and master clock mode
2021-10-18 16:13:31 +03:00
Istvan Csomortani 5ac64b021f spi_engine_execution: Delete control loop-back in sdi_data_valid generation 2021-10-18 16:13:31 +03:00
sergiu arpadi 6570c23a76 axi_spi_engine: Add generic config params
The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
2021-10-18 16:13:31 +03:00
Istvan Csomortani f86ae28e50 spi_engine/data_reorder: Initial commit
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.

The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
2021-10-18 16:13:31 +03:00
Istvan Csomortani 6565c5d018 library/tb: Improve run_tb.sh 2021-10-18 16:13:31 +03:00
LIacob106 e34346360d scripts: Add logic for vivado version check 2021-10-12 14:34:11 +03:00
Laszlo Nagy 812baf9022 Revert "data_offload: Fix timing violation"
This reverts commit 1fe0d5f8e0.
2021-10-08 11:42:05 +03:00
Filip Gherman dbd5ffe4ed jesd204_rx: fixed makefile 2021-10-07 12:48:08 +03:00
Laszlo Nagy 0c6c28ed84 jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes 2021-10-06 15:49:56 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Laszlo Nagy 22e1366bfc jesd204/jesd204_rx: Define tie off values for unused ports 2021-10-05 14:09:51 +03:00
Laszlo Nagy aa93c17cdc jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation 2021-10-05 14:09:51 +03:00
Laszlo Nagy 1a9e7dbeb4 jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP 2021-10-05 14:09:51 +03:00
Laszlo Nagy 4d12c4d99a scripts/adi_xilinx_device_info_enc.tcl: Add Versal support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2b242bf06f scripts/adi_ip_xilinx.tcl: Enable auto family support
Some IPs like JESD link layer were marked as not supported on Versal devices by
the current flow while other not (e.g. TPL).
The auto family support seems to workaround this issue.
2021-10-05 14:09:51 +03:00
Laszlo Nagy d94ec80e08 Update README.md
Correct the  ZCU102 PL DDR memory controller interface width and speed based on available options of the MIG
2021-10-05 11:59:51 +03:00
David Winter 0e8f55b2d7 data_offload: Fix oversized inputs in TX mode
This commit fixes an issue in situations where we provide an oversized
transaction to the data offload in TX mode. Previously, the data offload
would stop accepting new data (wr_ready <= 0) after filling up the
internal storage, and get stuck waiting for the input transaction to
end, thus locking up the device.

This commit addresses that issue by allowing the data offload to consume
the full input transaction, even if the tail of the buffer will be
truncated in the output.

Signed-off-by: David Winter <david.winter@analog.com>
2021-09-29 18:33:11 +03:00
Filip Gherman 7ed4955661 axi_adxcvr_ip.tcl util_adxcvr_ip.tcl: Fixed asynchronous resets critical warnings in XCVR 2021-09-28 04:53:02 +03:00
stefan.raus cfe0c0ced5 adi_project_xilinx.tcl, adi_ip_xilinx.tcl: update version to 2021.1
Update vivado version from 2020.2 to 2021.1 in projects and library scripts.
2021-09-24 12:11:11 +03:00
Mihaita Nagy 1fe0d5f8e0 data_offload: Fix timing violation 2021-09-22 12:18:33 +03:00
David Winter cdb9a0af2b data_offload: Add sync to cyclic mode
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-21 09:06:03 +03:00
AndreiGrozav 76cd5581bc axi_pwm_gen: Add config in soft reset option 2021-09-17 11:50:46 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Robin Getz b38747cefc Make system: Be explicit in license that cover the make/build system
The build system is covered under a 1 Clause BSD license. Make sure
users are aware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:50:53 +03:00
Robin Getz 12a3f8799e JESD204 Interface Framework : add logo
Add a small logo for branding purposes.

Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:49:52 +03:00
David Winter 1766b42a93 ad_mem_asym: Add option to control cascade layout
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-15 12:27:49 +03:00
Iacob_Liviu 6763ddcda9 spi_engine_execution: Fix cs signal generation
The cs signal can now accept the IOB TRUE attribute.
2021-09-13 11:39:02 +03:00
David Winter 0392013bd2 util_tdd_sync: Narrow scope of false path to D pin
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:24 +03:00
David Winter 7423ecae14 data_offload: Improve external synchronization
This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.

The default value retains the old behavior.

Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:01 +03:00
Filip Gherman 0372ce1821 axi_adxcvr:util_adxcvr: Correctly defined resets. 2021-09-08 11:51:59 +03:00
LIacob106 16a93a804b adrv9001[intel]: Add second pair of DMAs
fix observations for PR
2021-09-01 15:04:14 +03:00
alin724 f8c82c611d axi_adrv9001: Add support for symbol operation mode on Xilinx devices
Add CMOS support for the interface for the following symbol modes on Xilinx devices:

A              B  C       D                     E       F      G            H
CSSI__1-lane   1  16/8    80(SDR)/160(DDR)      80      -      SDR/DDR      SDR/DDR->4/2(C=16), 2/1(C=8)

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
2021-08-17 15:33:06 +03:00
Laszlo Nagy 8afc03abab jesd204/ad_ip_jesd204_tpl_dac: Intel: Add support for AD916x preset files 2021-08-16 07:22:50 +03:00
stefan.raus 1f24344620 Update Quartus version to 20.4
Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
2021-08-12 11:15:01 +03:00
David Winter 235542cac9 data_offload: Fix support for > 4 GiB of storage
This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.

Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.

Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 25038ccb4d data_offload: Fix MEM_SIZE parameter width
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00