The value of the HDL parameter NUM_OF_SDI can be read out from the
register at address 0x0C. The same register contains the value of the
DATA_WIDTH.
The register has the following bit layout:
[15: 0] DATA_WIDTH
[23:16] NUM_OF_SDI
[31:24] 8'b0
Forward the offload's sync_id to the register map, by defining an
additional AXI stream interface between the offload and axi_spi_engine.
The last sync_id of the offload module can read out from the
register 0x00C4. It also can generate and interrupt if the irq mask is
configured accordingly.
The commit 9ab88f1200 introduced a new
feature for the execution module, which provides the possibility to
delay the SDI line latch with one or more core clock cycle. Unfortunatly
the implementation was not correct and the SDI line was latched at the
wrong time.
This patch fix the aligment of the shift register and the SDI_DELAY parameter,
to latch the SDI line of the physical interface at the right time.
Improve the description of the feature.
xsim does not like if a register or wire is used before their
definition. Make sure the every register and wire is defined before it's
used the first time.
The pulse period had a fixed value. Therefore, in order to be able
to configure it from the software, a 32b register pulse_period_reg
was added in axi_spi_engine. Also, to generate the pulse, the
output register pulse_gen_loadc was added.
The ready signal of the SYNC interface should be always 1'b1,
regardless of ASYNC_SPI_VALUE.
Drive the ready with one in both branches of the ASYNC_SPI_CLK
generate block.
Add additional synchronization FIFOs to several interfaces of the
axi_spi_engine module, to prevent metastability and timing issues in
case when the system clock and the SPI clock are asynchronous.
There are devices where the SDO default state, between transactions, is
not GND, rather VCC.
Define a parameter, which can be used to set the default state of the
SDO line.
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top
fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]
The change excludes the generated system.v and Xilinx files.
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.
For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.
Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.
Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.
This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.
It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The external s_axi_{awaddr,araddr} signals that are connect to the core
have their width set according to the specified size of the register map.
If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently
is for many cores) the MSBs of those signals are left unconnected, which
generates a warning.
To avoid this make sure that the signal width matches the declared register
map size.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Istvan Csomortani
Arpadi
Stanca Pop
Adrian Costina
Lars-Peter Clausen
Laszlo Nagy
AndreiGrozav