For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
dev_new_device^[[m"
The above escape codes will mess up a terminals color scheme when this
information is read from sysid and displayed on a terminal.
Use --no-color flag to fix this issue.
New version of Quartus Standard for de10nano and sockit was changed
to 21.1.
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.
* library/axi_ad777x: Initial commit for Xilinx and Intel
* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Increased the Microblaze performance for the VCU118 carrier:
- Increased the size of Instruction Cache and Data Cache to 64kB
Increased the Microblaze clock frequency:
- Using the DDR4 Controller to generate a new sys_mb_clk of 214 MHz to drive all the Microblaze interfaces at higher frequencies
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Created a virtual clock to constrain cnv_en.
Given that the cnv_en should be asserted only once per 8 clock
cycles and only the rise edge is of interest, we can constrain
the path as multicycle path.
Because the inferface signals which pass through the eval board's
Arduino connector are connected to level shifters the design
will not work at the maximum clk frequency of 48MHz. The maximum
tested frequency is 24MHz.
AndrDragomir
LIacob106
Laszlo Nagy
Ionut Podgoreanu
AndreiGrozav
Iulia Moldovan
ladace
PopPaul2021
Laszlo Nagy
Sergiu Arpadi
Filip Gherman
alin724
Adrian Costina
Stanca Pop