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Author SHA1 Message Date
AndrDragomir 72378a6d4a projects: Add fmc connection files for eval boards 
Creating a new eval board fmc file:
  - docs: Open FMC_eval_board_template.xlsx
  - follow the instructions on the first sheet
 2022-09-20 14:11:08 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file 
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
 2022-08-08 13:52:54 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
PopPaul2021 0b8585a6f1
PN mismatch DAQ2, DAQ3 and FMCJESDADC1 fix (#950) 
The AD9680 is a dual 14-bit ADC.
Software sets the output format to offset binary before performing the PN tests.
 2022-06-02 14:09:36 +03:00
Dan Hotoleanu f34b561e19 daq3: Parameterize JESD204 configuration values 
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2022-01-31 10:47:01 +02:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory 
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
 2021-11-10 14:01:06 +02:00
LIacob106 58c1d2e3b2 projects: fixed xcvr clocks that generated critical warning 2021-11-09 12:40:14 +02:00
LIacob106 d4126739b4 projects: remove hardcoded div_clk from xcvr 2021-10-27 12:11:22 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Adrian Costina b080b52a14 daq3:zcu102: Connect overflow pins for the AD9680 TPL 2020-11-11 14:24:02 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
Adrian Costina 83cebe899f daq3: Update projects to the new TPL 
Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
 2020-10-21 18:59:37 +03:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Istvan Csomortani 9ee0f09078 daq3:qsys: Activate input pipeline stage for AD9680's JESD interface 2020-09-09 14:15:37 +03:00
Istvan Csomortani 02ada3bbf7 a10gx: Delete input/output delay definitions 
All input and output delays should be referenced to a virtual clock.

If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
 2020-08-11 10:14:18 +03:00
Istvan Csomortani f1a0946a5d daq3: Delete redundant timing constraint 
Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
 2020-08-11 10:14:18 +03:00
Laszlo Nagy 88e80f604e daq3:zcu102: fix GPIO double drive 2019-11-26 14:41:19 +02:00
Laszlo Nagy e22016de4c adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters 
Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
 2019-10-08 10:38:46 +03:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani 04ce10a570 cosmetics: Change Altera to Intel in comments 2019-06-29 06:53:51 +03:00
Istvan Csomortani 6e6f1347d7 project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani ec67a381e4 adi_project: Rename the process adi_project_altera to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Istvan Csomortani f22f448d4b daq3:vcu118: Delete constraint related to smart connect 
Apparently this constraint will cause more harm than good. The tool will
try to prevent an invalid hold violation by increasing the net delay,
causing a setup violation on the same path. (inside the smart connect)

See more info here:
https://forums.xilinx.com/t5/AXI-Infrastructure/Smartconnect-and-Synchronous-Clock-Domain-Crossing-Issues/td-p/904824
 2019-06-27 13:47:24 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 2019-06-11 18:13:06 +03:00
Laszlo Nagy 6c6d14722d daq3:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy 7f16f823ff Revert "axi_dmac: add tlast to the axis interface for Intel" 
This reverts commit e2c75c015f.
 2019-05-16 13:27:19 +03:00
Adrian Costina f5ed5def27 daq3: vcu118 initial commit 2019-04-17 14:24:35 +03:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters 
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
 2019-03-30 11:26:11 +02:00
AndreiGrozav 2d825d8b7c daq3_zc706: Change implementation strategy 2019-02-12 10:43:46 +02:00
Laszlo Nagy 27f1e4eaed daq3: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy d8e11cfce5 daq2/3: update DAC TPL base addresses 
The TPL for DACs can be relocated to addresses which match the software
expectations.
 2018-12-04 14:02:22 +02:00
Lars-Peter Clausen 1375dcfeaa daq3: Use new pack/unpack infrastructure 
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-11-28 11:33:11 +02:00
Istvan Csomortani cff8341c18 daq3/zcu102: Add custom configuration for CPLL 
To support 12.33 Gbps add a custom configuration for the CPLLs.
 2018-10-04 14:37:02 +03:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines 
Create loopback on unused GPIO lines since Linux may rely on it.
 2018-10-04 14:19:37 +03:00
Istvan Csomortani a387018f7a daq3:kcu105: Performance_ExploreWithRemap results the highest WNS 2018-08-23 18:41:48 +03:00
Adrian Costina db51fb2829 daq3: ZCU102: Remove Offload FIFO for ADC path. 
DAC FIFO cannot be increased because of timing violations
 2018-08-23 18:06:32 +03:00
Adrian Costina 563710e904 daq3: ZCU102: Fixed system_top to be similar with ZC706. Updated constraints to specify exactly transceiver pin locations 2018-08-23 18:06:32 +03:00
Istvan Csomortani 2293374307 adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs 
The affected projects are:
  - FMCADC2/VC707 - 16Mb
  - FMCADC5/VC707 - 16Mb
  - DAQ2/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ2/KC705  - ADC@4Mb and DAC@4Mb
  - DAQ2/VC707  - ADC@8Mb and DAC@8Mb
  - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
  - DAQ3/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
  - ADRV9371x/KCU105 - DAC@8Mb
  - ADRV9371x/ZCU102 - DAC@16Mb
 2018-08-21 11:44:05 +03:00
AndreiGrozav 4ddbb57749 daq3, fmcomms2/5: Cosmetic update only of the xdc files 2018-08-13 17:45:53 +03:00
AndreiGrozav c8fec4f70e daq3,fmcomms2/5 on zcu102: Fix warnings 
DIFF_TERM is not supported in UltraScale devices.
 2018-08-13 17:45:53 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero 
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
 2018-08-10 17:00:11 +03:00