3 Commits (74089397b35e0325099f40e0e7576c0b6a50c25b)

Author	SHA1	Message	Date
Iulia Moldovan	c9a7d4d927	Add copyright and license to .tcl, .ttcl files ... Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>	2023-07-25 15:22:26 +03:00
Bogdan Luncan	72313df81f	Updated the makefiles to build the projects in subdirectories based on the build parameters. ... Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>	2022-11-14 09:38:42 +02:00
Laszlo Nagy	0dd3173547	adrv9001/zc706: Initial commit ... The project supports CMOS interface only. VADJ on the ZC706 must be programmed to 1.8V Instructions can be found here: https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086	2021-03-03 09:03:03 +02:00