68461110aa
Replace link in license header from master to main
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
1cac2d82e1
Add copyright and license to .xdc files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
830b5aecb6
projects: 9009: system_project.tcl: List configs as comments
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Add a list with make commands with the proper parameters for each devicetree
availible at the moment.
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
2023-05-12 14:17:05 +03:00
db94628cc6
library & projects: Update Makefiles
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
9b8604b9a2
adrv9009/zc706: Add clkgen div to match the desired freq
2023-01-26 15:36:45 +02:00
72313df81f
Updated the makefiles to build the projects in subdirectories based on the build parameters.
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Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.
Note that the 'JESD' and 'LANE' words from the parameter names are stripped.
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
4bd55dc5c2
adrv9009/zc706: Hook up ref clock from IBUFDS_GT
2022-02-15 11:09:37 +02:00
4ec8797c7c
adrv9009: Parameterize JESD204 configuration values
2022-01-13 10:15:05 +02:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
32eeedb660
makefile: Update makefiles
2020-05-07 08:41:49 +01:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
78afe38a3f
adrv9009: Add decimation and interpolation filters
2019-08-20 16:24:47 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
0e750bea42
adrv9009: Fix dma_clk tree
2019-06-11 18:13:06 +03:00
70b7d69ff8
whitespace: Delete all trailing white spaces
2019-06-07 10:20:15 +03:00
3183fbf226
adrv9009: update adcfifo/dacfifo
2019-01-23 14:45:45 +02:00
0b66b39352
adrv9009/zc706: make SPI selection consistent
2018-12-21 17:32:48 +02:00
3d7a376f8b
Makefile: update makefiles
2018-12-21 17:32:48 +02:00
c9f1c92eaa
adrv9009: use generic TPL
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Make the block design parametrizable.
Limitations:
F = 1,2,4
2018-12-21 17:32:48 +02:00
47093775ae
adrv9009/zc706: top level cleanup
2018-12-21 17:32:48 +02:00
8adc285eab
adrv9009/zc706: fix location constraints
2018-12-21 17:32:48 +02:00
7a5a8c5340
Revert "adrv9009: Removed ZC706 based project"
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This reverts commit 7e7f75c0270bb6793bedb339f62b67bab9d77a6e.
2018-12-21 17:32:48 +02:00
4999a52f87
adrv9009: Removed ZC706 based project
2018-05-14 11:36:31 +03:00
e4d579726d
Renamed ad9379 to adrv9009
2018-04-26 18:19:11 +03:00
Iulia Moldovan
LIacob106
Bogdan Luncan
Laszlo Nagy
Filip Gherman
Adrian Costina
Sergiu Arpadi
Istvan Csomortani
AndreiGrozav