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16 Commits (74089397b35e0325099f40e0e7576c0b6a50c25b)

Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 15:22:26 +03:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters. 
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2022-11-14 09:38:42 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani 0e750bea42 adrv9009: Fix dma_clk tree 2019-06-11 18:13:06 +03:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters 
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
 2019-03-30 11:26:11 +02:00
Laszlo Nagy 3183fbf226 adrv9009: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy c9f1c92eaa adrv9009: use generic TPL 
Make the block design parametrizable.
Limitations:
  F = 1,2,4
 2018-12-21 17:32:48 +02:00
Istvan Csomortani 559e00fd75 adrv9009/zcu102: Increase DAC buffer depth to 18Mb 2018-10-11 16:57:30 +03:00
Adrian Costina e982232d75 adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs 2018-06-12 23:53:56 +03:00
Adrian Costina 801351d93c adrv9009: Increase sys_dma_clk to 325MHz. At 333 MHz, there are timing violations 2018-06-12 23:53:56 +03:00
Adrian Costina cc18f76e3b adrv9009: Reduced DAC FIFO size, as it's not useful for real applications and the memory can be used in other parts of the design 2018-06-12 23:53:56 +03:00
Adrian Costina 65c765eb33 adrv9009: Increase DMA FIFO sizes 2018-06-12 23:53:56 +03:00
Adrian Costina e445fbe04f adrv9009: Improved data throughput and DAC FIFO size 
Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA
HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time.
HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller
All HPx and DMA buswidths have been increased to 128 bits
The HPx-DMA clock has been increased to 300 MHz
DAC FIFO address size has been increased to 17
 2018-05-14 11:33:04 +03:00
Adrian Costina e4d579726d Renamed ad9379 to adrv9009 2018-04-26 18:19:11 +03:00