d2e9b1fe03
rfsom: schematic changes
2015-02-18 14:32:04 -05:00
3113abf038
cftl_cip: Add gpio counter for CN0332
...
Add a counter core to the design, to support the CN0332 pmod with a speed sensor.
Change a naming for the custom cores.
2015-02-18 18:24:46 +02:00
9cdec38532
gt- report device type
2015-02-17 11:43:57 -05:00
2442b6e929
gt- report device type
2015-02-17 11:43:50 -05:00
fccadcec31
jesd_gt: lpm/dfe programmable
2015-02-13 11:33:25 -05:00
de043ce130
gt_channel: lpm/dfe programmable
2015-02-13 11:33:04 -05:00
870ebdb562
up_gt: support lpm mode
2015-02-12 16:21:11 -05:00
1e7c9a3924
gt_es: support lpm mode - 2/2
2015-02-12 16:20:43 -05:00
0a8e6f62ef
gt_es: support lpm mode - 1/2
2015-02-12 15:15:18 -05:00
c908cea801
Merge branch 'master' into dev
2015-02-09 10:01:39 +02:00
9e2e2ef44e
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:16 -05:00
e9231c8f36
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:14 -05:00
e111e1336e
conflicts-
2015-02-06 22:14:21 -05:00
8839c8b18c
xfer-logic: stretch toggles to allow capture
2015-02-06 22:07:00 -05:00
8050a14bd8
xfer-logic: stretch toggles to allow capture
2015-02-06 22:06:56 -05:00
518d842af9
upack: initial commit
2015-02-06 15:15:33 -05:00
2d607d765b
cftl_cip: Add a clock input to the device core, for the SPI clock.
...
This clock can be adjustable from the system_project.tcl
2015-02-04 14:55:17 +02:00
d02c21b426
util_pmod_adc: General update
...
Redesign the state machine, rename constant and variable names, add notes and description.
2015-02-04 14:49:16 +02:00
996e1b7970
rfsom: constraint updates
2015-02-03 14:20:34 -05:00
890bb1da75
daq2: Add support for VC707
2015-01-29 18:33:27 +02:00
fd2ab02174
cftl_std: Added in the constraint file comments regarding supported CFTLs
2015-01-29 16:27:43 +02:00
8ccab473eb
README.md: General update
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/dev branch supports Vivado 2014.4
2015-01-29 12:46:19 +02:00
d69d105b5d
vc707_common: Fix address mapping
...
The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
2015-01-29 12:22:06 +02:00
e8ff30119d
vc707_xdc: Delete unnecessary clock definition
2015-01-29 11:39:10 +02:00
6c8ea24f20
common: Update VC707 base design to 2014.4
2015-01-28 16:24:52 +02:00
e1d8dd10a9
daq2: Initial check in of the VC707 based project
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NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 16:24:06 +02:00
96899313d8
axi_dmac: Fix constraint
...
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
b10ba49425
axi_dmac: Fix constraint related issue
...
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
2015-01-23 18:44:17 +02:00
d5bd485624
axi_dmac: Fix eot issue under 2014.4
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Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
2015-01-23 18:39:33 +02:00
659e0cca4e
cftl_cip: Initial check in.
...
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
463a3bbc88
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 14:11:33 +02:00
9672271155
fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet
...
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
2015-01-23 13:30:56 +02:00
5a77ab0161
a5gt:common: Added phy reset signal from ethernet in pin assignments
2015-01-23 12:31:41 +02:00
050f17e034
a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2
2015-01-23 12:30:16 +02:00
d6499e202c
Merge remote-tracking branch 'origin/hdl_2014_r2' into dev
2015-01-15 15:48:36 -05:00
5a1819ed6e
fifo2s: qualify last with valid
2015-01-15 15:42:10 -05:00
8fedb5b41c
fifo2s: qualify last with valid
2015-01-15 09:34:43 -05:00
72e89852b6
daq2/kc705: 2014.4 updates
2015-01-14 12:58:08 -05:00
4d46c9a095
Merge remote-tracking branch 'origin/master' into dev
2015-01-13 13:44:14 -05:00
024d9e7309
replace export hardware -- hwdef/sysdef
2015-01-13 13:40:21 -05:00
03988f1c9f
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:20 -05:00
b595cce697
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:18 -05:00
b0b4bfe531
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:17 -05:00
47871287f3
kc705: Updated base project with linear flash. Updated all depending projects
2015-01-13 10:19:07 +02:00
623e732ee6
kc705: Updated base project with linear flash. Updated all depending projects
2015-01-13 10:07:51 +02:00
b9e2c5659f
fmcomms2: 2014.4
2015-01-09 14:12:54 -05:00
9e64df917c
daq2: 2014.4
2015-01-09 14:12:53 -05:00
65d9f08763
zc706: mig 2014.4
2015-01-09 14:12:52 -05:00
868df1aac8
zc706: mig 2014.4
2015-01-09 14:12:51 -05:00
0258afbadc
board: add ddr seg variable
2015-01-09 14:12:50 -05:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina