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Author SHA1 Message Date
Istvan Csomortani 80333573c7 ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint 
Add one clock cycle input delay for the SYSREF input,
to compensate the high propegation delay of device_clk_BUFG.
 2019-10-17 09:59:23 +03:00
Istvan Csomortani 03bec4b49c ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location 
In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a  global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.

Also, swap the ports in both ZC706 and A10SOC carriers.
 2019-10-17 09:59:23 +03:00
Istvan Csomortani b3e1cd2a15 ad_fmclidar1_ebz: Add support for ZCU102 2019-10-17 09:59:23 +03:00