cf5b9b51fd
adi_board.tcl : Fix spi ports and hp clocks
2014-04-11 15:31:12 +03:00
37e2059fd0
adi_board.tcl : General update
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- Split the adi_dma_interconnect to two procedure:
adi_dma_interconnect and adi_hp_assign
- Fix the adi_spi_core
- Fix the adi_interconnect_lite
2014-04-10 18:29:14 +03:00
5b0e37b97a
adi_project.tcl : Modify implementation strategy
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- Change implementation strategy to Performance Explore.
At some projects, this could prevent timing issues, it not
increase the overall implementation time in a dramatic way.
2014-04-07 15:02:38 +03:00
8deb36ce08
adi_board.tcl: All procedures works on Zynq/Microblaze
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General patch for the integration procedures. Tested on kc705 and
zed.
2014-04-01 16:19:24 +03:00
4ef88a3bed
adi_board.tcl : Patch for adi_spi_core process
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- Fix indentation
- Pacth for adi_spi_core process
2014-03-31 16:41:07 +03:00
7f4f200fce
Project scripts: Initial check in of adi_board.tcl
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The script contains integration tcl processes.
2014-03-26 19:08:56 +02:00
698e9f4757
Added phys_opt_design step for fixing timing
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The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
2014-03-19 16:42:44 +02:00
7a6ce70e19
Fix default repository path for adi_project.tcl
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Projects can be build by running 'source system_project.tcl' in
Vivado Tcl console.
2014-03-13 10:28:16 +02:00
f3ae57a53e
global clock and reset names
2014-03-11 09:57:59 -04:00
793bf2f350
Change the adi_project_run process to prevent "const_type UCF" issue
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- Set the constraint type to XDC before run the synthesis
2014-03-07 11:06:11 +02:00
350ec5e633
changed path settings
2014-03-03 10:06:36 -05:00
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00
Istvan Csomortani
Adrian Costina
Rejeesh Kutty