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2519 Commits (778efd7c80df8e8da6fe581703f1af07bc66623c)

Author SHA1 Message Date
Adrian Costina 778efd7c80 axi_ad9152: Add altera IP description 2016-08-16 17:52:05 +03:00
Adrian Costina 108870a2dc kcu105: Don't use phy reset automation, as it's not supported for KCU105 2016-08-08 17:53:32 +03:00
Rejeesh Kutty 02fcba1c96 dacfifo- fix constraints 2016-08-02 16:30:30 -04:00
Rejeesh Kutty 26a3e67a82 adcfifo- fix constraints 2016-08-02 16:30:14 -04:00
Lars-Peter Clausen 6cd0d8a412 axi_dmac: Don't add CDC constraints when all clocks are synchronous 
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-08-02 19:27:21 +02:00
Istvan Csomortani 9915234cb0 util_dacfifo: Add constraints file 2016-07-28 15:43:35 +03:00
Istvan Csomortani 17722e9dfa daq2/common: Add util_dacfifo/dac_xfer_out control 2016-07-28 15:43:35 +03:00
Istvan Csomortani 66c02a10de util_dacfifo: Add dac_xfer_out control 
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
 2016-07-28 15:43:35 +03:00
Istvan Csomortani c2ee311ad4 util_dacfifo: Add a bypass option to the FIFO 2016-07-28 15:43:35 +03:00
István Csomortáni dca7334960 Merge pull request #19 from mfornero/hdl_2016_r1 
up_axi: Same cycle BVALID/READY fails on Altera
 2016-07-28 15:31:47 +03:00
Adrian Costina b611240d46 kcu105: Update base project to 2015.4.2 
- change part to revision 1.1 of the board
 2016-07-22 17:50:18 +03:00
Matthew Fornero aa3a821456 up_axi: Same cycle BVALID/READY fails on Altera 
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
 2016-07-19 09:50:43 -07:00
Lars-Peter Clausen b2203cacce adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic 
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-07-14 11:33:56 +02:00
Lars-Peter Clausen fe08222bdf Enable bitstream compression for Xilinx projects 
Enabling bitstream compression reduces the size of the generated bitstream.

This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.

On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.

The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.

When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.

Initial tests show a reduction of a round 50% in size for most ADI
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-07-14 11:40:04 +03:00
Adrian Costina 130bfdd408 motcon2_fmc: Update to revision C 2016-06-13 15:42:25 +03:00
Adrian Costina df04eae2a7 motcon2_fmc: Sync transfer start for the current monitor DMAs, because there are 3 channels active usually 2016-06-13 15:41:02 +03:00
Adrian Costina 334aaeb59a daq3: Added a10gx project 2016-06-08 14:13:53 +03:00
Adrian Costina 90aa27c3b0 daq3: Make daq3_spi module more generic 2016-06-08 14:11:34 +03:00
Adrian Costina 249cb3fb57 axi_ad9152: Added arprot and awprot signals 2016-06-08 14:09:16 +03:00
Istvan Csomortani dbebcb7968 README.md: Update the README 
(cherry picked from commit 7b01cd9eca)
 2016-05-26 09:09:42 +03:00
Rejeesh Kutty 136a86adae a10gx/base: set gpio to 32 2016-05-18 15:26:12 +03:00
Rejeesh Kutty 93b338eea4 a10gx/base: separate gpio in/out 2016-05-18 15:26:03 +03:00
Adrian Costina a51dd941a9 a10gx: Updated base design to include MMU 2016-05-18 11:44:43 +03:00
Rejeesh Kutty 33ceb5e673 daq2/a10gx: 10AX115S3F45E2SGE3 version 2016-05-17 22:56:04 +03:00
Rejeesh Kutty 35a98550d9 daq2/a10gx: 10AX115S3F45E2SGE3 version 2016-05-17 17:16:33 +03:00
Rejeesh Kutty 00d9d4484e daq2/a10gx: 10AX115S3F45E2SGE3 version 2016-05-17 17:16:25 +03:00
Adrian Costina c7d3560cb7 arradio: Connect I2C peripheral to the arradio board. Used HPS I2C 2016-05-11 14:20:21 +03:00
AndreiGrozav c291f8f107 daq1: Updated design to 2015.4 2016-04-14 23:36:47 +03:00
AndreiGrozav 469b4ea5e8 fmcadc5: Updated design to 2015.4 2016-04-14 23:18:23 +03:00
AndreiGrozav 62bd057106 fmcadc5/common: Update common design to 2015.4 2016-04-14 23:01:38 +03:00
AndreiGrozav 6fe41ebb08 axi_hdmi_tx: Upgrade hdmi clipping process 
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
 2016-04-12 22:01:07 +03:00
AndreiGrozav 21208ca208 Makefiles: Update Makefiles 2016-03-31 12:37:47 +03:00
Adrian Costina 657144d9a7 a10gx: Updated base design and DAQ2 to the new revision of the a10gx board 
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
 2016-03-28 13:21:36 +03:00
AndreiGrozav 7c2f34549b motcon2_fmc: Update common design to 2015.4 2016-03-23 10:27:07 +02:00
AndreiGrozav b31cdac6bd util_gmii_to_rgmii: Updated to 2015.4 
The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
 2016-03-23 10:14:18 +02:00
AndreiGrozav 769fecbe00 axi_i2s_adi: Fixed clock association 2016-03-21 20:18:45 +02:00
AndreiGrozav 714caa964c usdrx1: Update common design to 2015.4 2016-03-18 16:29:43 +02:00
AndreiGrozav 05f4f3ac09 usb_fx3: Update common design to 2015.4 2016-03-18 16:16:38 +02:00
AndreiGrozav 24fdd2b9b7 pzsdr/ccpci: Update common design to 2015.4 2016-03-18 15:30:10 +02:00
AndreiGrozav f8b155faab pzsdr/ccfmc: Update common design to 2015.4 2016-03-18 15:28:56 +02:00
AndreiGrozav d567af54ef imageon: Update common design to 2015.4 2016-03-18 15:27:31 +02:00
AndreiGrozav 995debedce fmcomms2: Update common design to 2015.4 2016-03-18 15:26:52 +02:00
AndreiGrozav b555be25d5 kcu105: Update common design to 2015.4 2016-03-18 15:22:42 +02:00
AndreiGrozav 412013d939 adv7511: Update common design to 2015.4 2016-03-18 15:01:25 +02:00
AndreiGrozav 6d277733d5 axi_spdif_rx: Fixed the clock association 2016-03-18 13:58:13 +02:00
AndreiGrozav 28990e362a axi_spdif_tx: Fixed the clock association 2016-03-18 13:31:06 +02:00
AndreiGrozav d355aa0ea6 daq3/zc706: Updated design to 2015.4 2016-03-17 11:46:48 +02:00
AndreiGrozav 012b095006 daq3: Updated common design to 2015.4 2016-03-17 11:44:27 +02:00
AndreiGrozav 38c3f7474a ad6676: Updated common design to 2015.4 2016-03-17 11:40:46 +02:00
AndreiGrozav abc03fff2c fmcomms7: Updated design to 2015.4 2016-03-17 09:11:41 +02:00