Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
It also allows to configure the fixed delay value so that no additional constraints are needed
The default value of 18 seems to work very well(450mbps tx / 640 mbps rx) on the motor control platform used for tests
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
This core has been superseded by the SPI Engine framework in combination
with the axi_generic_adc core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.
Currently included are four components:
* SPI Engine execution module: The excution module is responsible for
handling the low-level physical interface SPI logic.
* SPI Engine AXI interface module: The AXI interface module allows
memory mapped acccess to a SPI bus control stream and can be used to
implement a software driver that controls the SPI bus.
* SPI Engine offload module: The offload module allows to store a
predefined SPI Engine command and data stream which will be send out
when a external trigger signal is asserted.
* SPI Engine interconnect module: The interconnect module allows to
combine multiple control streams into a single stream giving multiple
control modules access to a execution module.
For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The axi_generic_adc core is a simple core that doesn't do much more then
implementing the AXI ADC register map and routing the enable and overflow
signals to the farbic.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
The constraints processing order changed to "late" instead of "early", in order for all the clocks in the system to be already created when the IP constraints are applied
While the reset for the memory mapped AXI master is synchronous to some
clock it is not necessarily synchronous to the clock used for that
interface. So always generate a local reset signal to avoid problems that
could result from this.
While we are at it also update the code to only generate a local reset if
the interface is asynchronous to the register map, otherwise use the
register map reset.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Ignore the timing path from the current DMA address to the register map,
this is just a debug signal at the moment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
If the internal FIFO is larger than one block ram there will be multiple
BRAMs called ram_reg[0], ram_reg[1]. Modify the BRAM constraint rule so that
it matches these as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Set the ASYNC_REG property on the bit synchronizer CDC control regs. This
hint to Vivado that the registers are used for CDC purposes.
Also use -datapath_only for the set_max_delay constraints on the CDC data
path to remove the hold time requirement.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the axi_hdmi_tx core constraints marks all its clocks asynchronous
to all other clocks in the system. This is a bit unfortunate as these
constraints are not restricted to the axi_hdmi_tx, but affect all cores in
the system, some of which might actually have timing constraints on CDC
paths.
The proper way to fix this is to add constraints for the axi_hdmi_tx core
CDC paths. For now only mark the interface clock asynchronous to the HDMI
clock, as this is easy to do and an improvement over the current situation,
as other cores are no longer affected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The src_response_fifo has been removed from the design, but we still need to
assert the ready and empty control signals for things to work properly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We really only want to apply the CDC constraints if the clocks are actually
asynchronous. Unfortunately we can't use if ... inside a xdc script. But we
can use expr which has support for a ? b : c if-like expression. We can use
that to create helper variables that contains valid clock when the clock
domains are asynchronous or {} if they are not. Passing {} as
set_false_path/set_max_delay as either the source or destination will cause
it to abort and no constraints will be added.
Also add -quiet parameters to avoid generating warning if the constraints
could not be added.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
All the FPGA internal control signals are active high, using a active low
reset inserts a extra invert LUT. By using a active high reset we can avoid
that.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
* Generate a separate synchronous reset for the data clock domain.
* Add missing stage to toggle synchronizers.
* Give a common prefix to CDC elements and add the proper constraints to the
XDC file
* Remove some unnecessary resets
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Use common prefix for CDC elements and add the proper constraints to the XDC
file. And add a missing stage to the toggle synchronizers.
Also drop a some unnecessary resets.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The only time we must not write to the FIFO is when it is full as this will
overwrite the first sample. Under all other conditions it is ok to write
data. If that data is invalid it will be overwritten when valid arrives.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Instead of just marking all clock domains as asynchronous set the
appropriate constraints for each CDC path.
For single-bit synchronizers use set_false_path to not constraint the path
at at all.
For multi-bit synchronizers as used for gray counters use set_max_delay with
the source clock period domain to make sure that the signal skew will not
exceed one clock period. Otherwise one bit might overtake another and the
synchronizer no longer works correctly.
For multi-bit synchronizers implemented with hold registers use
set_max_delay with the target clock period to make sure that the skew does
not get to large, otherwise we might violate setup and hold time.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In order to be able to use get_clocks in a constraint file the constraint
file needs to run after the constraint file that creates the clock. Allow to
specify the processing order when adding a constraint file to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a room output on the input side that reports how many free entries the
FIFO has and a level output on the output side that reports how many valid
entries are in the FIFO.
Note that the level output is only accurate if the output of the FIFO is not
registered, otherwise it might be off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a option to specify whether the FIFO should have a registered output
stage or not. This is useful if the user wants to implement that stage
itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
Add support for specifying whether the lsb of the larger bus are mapped to
the first or the last beat on the smaller bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Update the axi_repack core so it can handle non power-of-two ratios between
the input and output stream width. The ratio still needs to be a integer
though.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.
Also rename it to util_axis_resize to better reflect its function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a helper function that allows to add dependencies to IP cores to the
current IP core, this makes it possible to use a module from the other IP
without having to add the file itself to the current core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Instead of using a path relative to the current working directory use a path
relative to the location of the adi_env.tcl script.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.
Using interface pins also unclutters the connections in the Vivado block
design view a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.
Using interface pins also unclutters the connections in the Vivado block
design view a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Initialize ip_repo_paths so that when building a peripheral we have access to the interface definitions stored in the repository.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.
This makes the function more flexible and e.g. allows to handle buses from other vendors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The util_sync_reset peripheral hasn't been used in a while and will not be
used in new projects. So remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.
To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.
So just stop generating burst requests once the DMAC is being disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
Istvan Csomortani
Lars-Peter Clausen
Rejeesh Kutty
Adrian Costina