31ab81d627
a5gt: Updated ethernet clock constraints
2015-07-27 16:02:51 +03:00
797d679c72
fmcomms2: Updated c5soc project with the latest cores. Tested with Quartus 15.0
2015-07-24 16:43:33 +03:00
623c3dc333
axi_ad9361: Updated altera core by including tdd related files. Removed deleted ports
2015-07-24 16:41:41 +03:00
caca364c61
ad9652- iqcor iqsel changes
2015-07-24 08:35:13 -04:00
144b8f7383
ad9643- iqcor iqsel changes
2015-07-24 08:34:52 -04:00
816238bb6c
fmcjesdadc:A5gt, decreased destination bus width for DMAs to 256. Increased DMA FIFO to 32
...
With lower buswidth, if all 4 channels are captured some samples are lost
With fifo size of 64, there are timing violations in the DMAC
With this configuration, 65536 samples could be captured from all 4 channels with no sample lost
Because of the DMAC destination bus is 256, the number of samples to be captured must be a multiple of 16, otherwise the system will freeze. This will be corrected in software
2015-07-24 15:31:19 +03:00
43946a54a4
axi_dmac: Added C_FIFO_SIZE parameter
2015-07-24 15:30:10 +03:00
649297a0e3
ad_iqcor- changes
2015-07-23 16:20:46 -04:00
cd5ce3349f
iqcor- move i/q sel inside the module
2015-07-23 15:55:45 -04:00
289e73660b
removed- xcvr is now part of qsys
2015-07-23 15:26:51 -04:00
fb648ab6f5
moved to qsys
2015-07-23 15:26:21 -04:00
3ccf1bef36
base system modifications
2015-07-23 15:23:10 -04:00
a1733238df
fmcjesdadc1- base/board split up
2015-07-23 15:21:53 -04:00
3ea60bca5d
fmcjesdadc1: a5gt, design working with quartus 15.0
...
- added cpack to the design
- removed 166 MHz clock as it is not needed. DMA destination is 512 bits
- removed clock bridge between DMA and DDR
2015-07-23 18:11:53 +03:00
3d1ffe7bd2
util_cpack: Added reset interface
2015-07-23 17:01:53 +03:00
f7d28e0944
axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them
2015-07-23 17:01:02 +03:00
41e9a34886
axi_ad9250: Changed Altera interface specification to be compatible with upack
2015-07-23 16:59:57 +03:00
d8e2196c75
fmcjesdadc1- board qsys
2015-07-22 15:44:04 -04:00
d66387f482
fmcjesdadc1- board qsys
2015-07-22 15:23:39 -04:00
3e2712cf18
a5gt-base: initial updates
2015-07-22 15:22:22 -04:00
64070b6f27
a5gt- base system
2015-07-22 15:04:59 -04:00
901bcb2c06
dma- constraints modifications
2015-07-22 12:46:06 -04:00
3d7afb8fc5
jesd-xcvr: constraints modifications
2015-07-22 12:46:06 -04:00
6352884398
jesd-xcvr: common align function
2015-07-22 12:46:06 -04:00
a4461545fa
axi-ip: constraints - altera
2015-07-22 12:46:06 -04:00
ac39329046
axi_spdif_rx: Fix the pl330_dma control path
...
- fix pl330_dma control path
- delete unused control_reg bits
- change the port name spdif_rx_i_osc to spdif_rx_i_dbg
- version_reg is read only
2015-07-22 17:59:52 +03:00
b325c0fc01
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:22:07 +03:00
28aea82952
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:16:04 +03:00
b4eac232db
a10gx- move cores inside qsys
2015-07-21 11:06:45 -04:00
fcc298d837
a10gx- move cores inside qsys
2015-07-21 11:06:17 -04:00
559893c0a3
altera- obsolete cores
2015-07-21 11:04:26 -04:00
b3102b5095
daq2/a10gx-- xcvr+base changes
2015-07-21 11:01:45 -04:00
86dabbe5fc
jesd-align-- xilinx/altera merge
2015-07-21 10:57:00 -04:00
3a4581a8df
axi-xcvr: removed xcvr compoents
2015-07-21 10:56:04 -04:00
264f9ffbfc
ip_alt- avalon/reset definitions
2015-07-21 10:55:13 -04:00
445c4c835d
daq2-bd: xcvr components
2015-07-21 10:54:23 -04:00
08e46c5ff2
a10gx-base: data-master connections
2015-07-21 10:53:54 -04:00
97b8468819
daq2- constraints
2015-07-20 09:32:17 -04:00
1d6a77049d
daq2- base/board split
2015-07-20 09:31:57 -04:00
4b8d764852
daq2- base system modifications
2015-07-20 09:31:44 -04:00
da2e7acacb
daq2- separate base/board systems
2015-07-20 09:31:15 -04:00
2f53dc4412
daq2- board system only
2015-07-20 09:30:32 -04:00
a87b8fbf94
a10gx- base system only
2015-07-20 09:29:30 -04:00
3101045109
qsys- library group
2015-07-17 10:07:15 -04:00
80dc3bf92f
daq2/a10gx: remove signal tap
2015-07-16 14:59:01 -04:00
1de74c0267
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-16 18:22:05 +03:00
c949482574
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-16 18:21:49 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
Adrian Costina
Rejeesh Kutty
Istvan Csomortani