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2519 Commits (778efd7c80df8e8da6fe581703f1af07bc66623c)

Author SHA1 Message Date
Istvan Csomortani 0ffb1095d9 Revert "ad9625_vc707: Fix source file definition" 
This reverts commit 6c80d88a0c.
 2014-11-06 14:59:08 +02:00
Istvan Csomortani 6b7fccf56b ad9625_fmc: Preserve the IRQ layout 2014-11-06 12:20:26 +02:00
Istvan Csomortani c6df568a00 Revert "ad_interrupts: Initial check in." 
This reverts commit b254380338.
 2014-11-06 12:16:52 +02:00
Rejeesh Kutty b11d80ed98 ad_rst: changed to dual stage 2014-11-05 16:48:02 -05:00
Rejeesh Kutty 74ec396b27 ad_rst: ultrascale -dual stage 2014-11-05 16:47:41 -05:00
Rejeesh Kutty 0425202da5 fmcadc3: compilation fixes 2014-11-05 11:59:10 -05:00
Rejeesh Kutty d69ccebbde ad9234: full 16bit samples 2014-11-05 11:59:08 -05:00
Adrian Costina fcd015305c ad9625x2_fmc: Updated vc707 project to include linear flash 2014-11-05 17:19:35 +02:00
Adrian Costina 4634a4f868 vc707: Added linear flash to the base design 2014-11-05 17:18:40 +02:00
acozma f1c5173a12 motor_control: Renamed the project to motcon1_fmc 2014-11-05 09:51:18 +02:00
Paul Cercueil 0f1bc27e27 fmcadc3: Connect adc_dwr and dma_ready to ILAs 
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
 2014-11-04 18:09:30 +01:00
Paul Cercueil d7ba7a95a6 fmcadc3: Update to use latest DDR3_fifo IP 
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
 2014-11-04 18:09:30 +01:00
Istvan Csomortani 6c80d88a0c ad9625_vc707: Fix source file definition 
The project using "p_sys_dmafifo" process, from sys_axi_dmafifo.tcl.
 2014-11-04 15:21:25 +02:00
Rejeesh Kutty 80646a641b ad9625x2_fmc: constraints order changes 2014-11-03 15:02:35 -05:00
Rejeesh Kutty 56e65f5926 ad9625x2_fmc: add dma fifo 2014-11-03 15:02:00 -05:00
Rejeesh Kutty 8c0782cb74 ad9625x2_fmc: constraints changes 2014-11-03 15:01:40 -05:00
Rejeesh Kutty beee377fb7 ad9625x2_fmc: interrupts fix 2014-11-03 15:01:15 -05:00
Rejeesh Kutty 8e6cb2bad4 ad9625x2_fmc: dma fifo additions 2014-11-03 15:00:51 -05:00
Lars-Peter Clausen 7ad9340992 pmod_ad7175: Connect gain control pin 
Connect the gain control pin to GPIO32 of the ZYNQ.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-11-03 15:00:02 +01:00
Paul Cercueil 4eea04cc9d fmcadc3: zc706: Fix DMA enable connection 
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
 2014-11-03 14:45:16 +01:00
Istvan Csomortani 57137df018 fmcjesdadc1_zc706: Interrupt update 2014-11-03 13:02:09 +02:00
Istvan Csomortani 4f815b99a1 kc705_base: Fix sys_concat_intc input connections 
All the unused input pins need to be connected to ground.
 2014-11-03 13:02:08 +02:00
Istvan Csomortani 8ef3eada7d adv7511_ac701: Interrupt update 2014-11-03 13:02:07 +02:00
Istvan Csomortani 98b92c4bc1 adv7511_kc705: Interrupt update 2014-11-03 13:02:06 +02:00
Istvan Csomortani 0246a40e28 adv7511_vc707: Interrupt update 2014-11-03 13:02:05 +02:00
Istvan Csomortani f7588131da ac701_base: Interrupt update 2014-11-03 13:02:04 +02:00
Istvan Csomortani b92636c6eb kc705_base: Interrupt update 2014-11-03 13:02:03 +02:00
Adrian Costina 25f37ffce7 usdrx1: Added cpld configuration files 2014-11-03 12:54:54 +02:00
Rejeesh Kutty 99ad286c41 kcu105: adv7511 updates 2014-10-31 13:28:17 -04:00
Rejeesh Kutty 8ed9d10502 ad9625_fmc: disable sync 2014-10-31 13:05:18 -04:00
Rejeesh Kutty 403fe1b373 wfifo: read only if ready is asserted 2014-10-31 13:05:17 -04:00
Adrian Costina 6f5a268909 fmcomms1: ZC706, updated project with latest constraints and interrupts 2014-10-31 17:59:56 +02:00
Adrian Costina 38652b1c3e axi_ad9643: Added constraint file 2014-10-31 17:57:47 +02:00
Adrian Costina 3e9ce71d21 axi_ad9122: Added constraint file 2014-10-31 17:56:56 +02:00
acozma a84397d345 motor_control: Changed the encoder pins mapping. 2014-10-31 17:37:28 +02:00
acozma 356e1c7ac1 motor_control: Changed the encoder pins mapping. 2014-10-31 17:08:18 +02:00
Adrian Costina 3c78d8fe58 ad9265_fmc: Added correct fifo to ILA. Updated interrupts 2014-10-31 14:49:29 +02:00
Adrian Costina 6fac294b6f fmcomms2: Updated zc706 project to new interrupt system 2014-10-31 14:15:29 +02:00
Istvan Csomortani 91ea11041d prcfg_mitx045: Upgrade of the project script. 
- the design using the common PN monitor
 - the first implemented logic will be the qpsk, to get a better result
 - cosmetic changes
 2014-10-31 12:18:00 +02:00
Istvan Csomortani d596d71285 prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator. 
This fix the wrong symbol mapping issue.
 2014-10-31 12:14:52 +02:00
Istvan Csomortani eb520b1f75 prcfg_qpsk: Major update 
Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
 2014-10-31 12:10:59 +02:00
Istvan Csomortani e450e78f13 prcfg: Update design to Vivado 2014.2 2014-10-31 12:05:19 +02:00
Istvan Csomortani 860a7caa56 prcfg: dac and adc to dma interface width is 64 2014-10-31 12:04:34 +02:00
Istvan Csomortani ea194755e1 prcfg: Upgrade the QPSK logic 
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
 2014-10-31 11:59:29 +02:00
Istvan Csomortani 16cdae3001 mitx045_base: Delete unnecessary timing constraints. 2014-10-31 11:50:49 +02:00
Istvan Csomortani 07673b673a adv7511_mitx045: Interrupt update 2014-10-31 11:46:27 +02:00
Istvan Csomortani 67bec719f7 mitx045_base: Interrupt update 2014-10-31 11:45:33 +02:00
Paul Cercueil b9f800ff65 fmcadc3: zc706: Fix connection to the system clock 
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
 2014-10-31 11:06:16 +01:00
Rejeesh Kutty 21f99b1c97 daq2: remove ila for kcu105 2014-10-30 15:26:29 -04:00
Rejeesh Kutty 56859ad4c9 sys_dmafifo: use internal memory 2014-10-30 15:26:28 -04:00