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3277 Commits (7876c8ffa4b18d557ece2f04e9ce145c1872b20c)

Author SHA1 Message Date
Lars-Peter Clausen 43c74bf55c axi_i2s: Tie-off optional inputs 
Tie-off all optional inputs to 0 so that they are driven to a defined value
when not used.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-11-18 15:01:26 +01:00
Lars-Peter Clausen 26907ef1fd axi_i2s: Remove duplicated clock interface association 
The I2S interface has a clock associated to it twice, this will generate a
critical warning when using the core, so remove one of them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-11-18 15:01:24 +01:00
Lars-Peter Clausen 0d75bcb606 pzsdr2: ccbox: Use DMA interface 0+1 for audio 
There is a bug in the ps7 component specification that causes critical
warnings to appear in the build log if DMA interface 0 is disabled, but any
other DMA interface is enabled.

Work around this issue by using DMA interface 0 and 1 instead of 1 and 2
for the I2S DMA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-11-18 14:03:46 +01:00
Rejeesh Kutty b62f60b0da pzsdr1/ccbox- updates 2016-11-17 16:14:28 -05:00
Rejeesh Kutty 935f8a5c7b pzsdr1/ccbox- constraints 2016-11-17 16:13:53 -05:00
Rejeesh Kutty 4f65bcb3b2 pzsdr1/ccbrk_cmos- updates 2016-11-17 15:32:49 -05:00
Rejeesh Kutty e85dd2740a pzsdr1/ccbrk_lvds- updates 2016-11-17 15:32:25 -05:00
Rejeesh Kutty a61da1d2ac pzsdr1/common- updates 2016-11-17 15:31:25 -05:00
Rejeesh Kutty aa02ca875f pzsdr1- common files 2016-11-17 13:40:25 -05:00
Rejeesh Kutty 8c25402d53 pzsdr1- common files 2016-11-17 13:40:04 -05:00
Rejeesh Kutty 4dae754287 pzsdr1- added readme 2016-11-17 11:29:01 -05:00
Rejeesh Kutty 778638a7a1 pzsdr2- make updates 2016-11-17 10:26:45 -05:00
Rejeesh Kutty 74bf4dfb80 pzsdr2- gpio- turn-around 2016-11-17 10:24:50 -05:00
Rejeesh Kutty d0166a4c7e ccbox- updates 2016-11-17 10:24:11 -05:00
Rejeesh Kutty c2b7cbd61b ccbox- constraints 2016-11-17 10:23:51 -05:00
Rejeesh Kutty 5e6b931150 ccbox- added 2016-11-17 09:28:33 -05:00
Rejeesh Kutty fb5d36b250 pzsdr2- update ccfmc 2016-11-16 16:27:41 -05:00
Rejeesh Kutty 95c44b687e pzsdr2- fmc/pci constraints 2016-11-16 16:27:41 -05:00
Rejeesh Kutty 11347c49be fmcomms11- device set to -3 2016-11-16 13:43:07 -05:00
Rejeesh Kutty b85a282748 fmcomms11- lane swap 2016-11-16 10:26:47 -05:00
István Csomortáni bdd14c3874 README: Delete second rule under headers 
By default there is a rule under each header, no need for another one.
 2016-11-16 11:04:43 +02:00
István Csomortáni 81e47edcd5 README: Set links for documentation 2016-11-16 10:57:39 +02:00
rejeesh kutty fabbe4981e Update README.md 
updated
 2016-11-15 16:15:55 -05:00
Rejeesh Kutty 538a1c977f pzsdr2: make files 2016-11-15 16:00:55 -05:00
rejeesh kutty 4905e80df8 Update README.md 
updated
 2016-11-15 14:16:46 -05:00
Rejeesh Kutty db243df97e pzsdr2- updates 2016-11-15 14:16:06 -05:00
AndreiGrozav 0897716167 fmcadc4: xcvr updates 2016-11-15 16:03:52 +02:00
AndreiGrozav cac4057449 daq2/common: Altera updates 2016-11-15 16:03:52 +02:00
Rejeesh Kutty cfd3ea61f1 pzsdr-to-pzsdr2 2016-11-14 14:12:22 -05:00
AndreiGrozav 9d6c93a5d8 Fix warnings 2016-11-14 15:17:15 +02:00
Istvan Csomortani 12d6e46ae7 clean: Delete deprecated source files 
The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located
at library/xilinx and library/altera.
The axi_jesd_xcvr was an early version of axi_adxcvr.
The register map is moved to the IP's directory.
 2016-11-14 10:43:46 +02:00
Rejeesh Kutty f64b44c8ac sdrstk2pluto- contents 2016-11-11 13:52:57 -05:00
Rejeesh Kutty 2ececad58c sdrstk-2-pluto 2016-11-11 13:49:04 -05:00
Adrian Costina c80033cb1b util_fir_int: removed s_axis_data_tvalid and updated sdrstk 2016-11-11 17:52:19 +02:00
Rejeesh Kutty e62fe0c086 fmcjesdadc1- a5gt/a5soc- sysclk is different 2016-11-11 10:34:18 -05:00
Adrian Costina 6f4dc92dd2 util_fir_int: Fix channel data assignment 2016-11-11 15:46:17 +02:00
Istvan Csomortani 7008c641b5 axi_adrv9371/zc706: Constraints update 
From source *jesd_rstgen* is a false path for TX and RX_OS too.
 2016-11-11 10:35:09 +02:00
Rejeesh Kutty 85eac8c811 fmcjesdadc1/a5*- updates 2016-11-10 16:57:06 -05:00
Rejeesh Kutty 959055bd54 common/a5gt- updates 2016-11-10 16:56:35 -05:00
Rejeesh Kutty 7a2c713a4e fmcjesdadc1/a5* - hdlmake.pl 2016-11-10 11:37:06 -05:00
Rejeesh Kutty c6730ab2d7 fmcjesdadc1/a5gt- updates 2016-11-10 11:36:41 -05:00
Rejeesh Kutty c207589f4b fmcjesdadc1/a5gt - qsys2tcl flow 2016-11-10 11:32:29 -05:00
Rejeesh Kutty 8af0731bb0 a5gt- qsys2tcl flow 2016-11-10 11:30:18 -05:00
Adrian Costina 7a606cbae1 sdrstk: Maximum clock frequency is 61.44 in CMOS mode 2016-11-10 17:45:35 +02:00
Adrian Costina 64d1d54ec0 util_fir_int: Update filter, as it's used with ad9361 in CMOS mode 2016-11-10 17:45:03 +02:00
Adrian Costina 66098b7ae7 util_fir_dec: Update filter, as it's used with ad9361 in CMOS mode 2016-11-10 17:43:04 +02:00
Adrian Costina d29ef14f36 sdrstk: Configured ad9361 in 1r1t mode 2016-11-10 17:06:42 +02:00
Istvan Csomortani a54092c9bb fmcjesdadc1: Update projects to xcvr framework 
This commit contains modifications for Xilinx only
 2016-11-10 10:59:52 +02:00
Istvan Csomortani 6073cdded4 axi_ad9250: Tie rx_valid to ground 2016-11-10 10:52:37 +02:00
Istvan Csomortani 8845aeb6ab axi_ad9250: Add missing file to Make and script 2016-11-10 10:48:46 +02:00