ce4f9bf906
up_dac_common: rename internal signals
2017-05-15 18:58:26 +03:00
d374f5b091
library/up_adc_common- add sref sync option
2017-05-10 14:33:56 -04:00
801fb2281e
util_pulse_gen: The valid period is stored in pulse_period_d
2017-04-27 11:28:24 +03:00
9cd218eb90
up_dac_common: Increase datawidth of dac_datarate
...
In case of high precision devices with just a simple SPI interface
for control and data, the effective data rate can be significatly
lower than the SPI clock, and more importantly there isn't any relation
between the two clock domain.
The rate is defined by a SOT (start of transfer) generator, which
initiates a SPI transfer. Taking the fact that the generator runs
on system clock (100 MHz), and the device can require smaller rate (in kHz domain),
the 7 bit dac_datarate register is just too small.
Therefor increasing to 16 bit.
2017-04-27 11:24:08 +03:00
d061104a3c
util_pulse_gen: Add configuration interface for 'pulse period'.
2017-04-27 11:21:12 +03:00
5d6b018b2b
ad9162- add iq swap
2017-04-26 20:54:47 -04:00
5fe7a1b100
axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass
2017-04-21 13:23:03 +03:00
931758b70c
ad_tdd_control: Optimize the burst_counter logic
...
The tdd_burst_counter should be in reset if the tdd_cstate
is not ON. (tdd counter is inactive)
2017-04-19 12:02:31 +03:00
ac5efc9adc
library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
2017-04-18 12:17:41 +02:00
9550c7f352
up_axi: Allow to configure AXI address width
...
Not all peripherals need the full address space. To be able to infer the
size of the address space of a peripheral allow the size of the AXI address
signals to be configurable rather than hardcoding its width to 32 bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
118dd18ba0
up_dac_common: Added clock enable control for the DAC cores
2017-04-18 12:17:40 +02:00
2296ef5882
up_adc_common: Added clock enable control for the ADC cores
2017-04-18 12:17:40 +02:00
957730c421
up_dac_common: Allow to disable GPIO registers
...
Not all peripherals use the GPIO register settings, but the registers still
take up a fair amount of space in the register map. Add options to allow to
disable them when not needed. This helps to reduce the utilization for
peripherals where these features are not needed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
0ae0da488b
up_adc_common: Allow to disable GPIO and START_CODE registers
...
Not all peripherals use the GPIO and START_CODE register settings, but the
registers still take up a fair amount of space in the register map. Add
options to allow to disable them when not needed. This helps to reduce the
utilization for peripherals where these features are not needed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:38 +02:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
ebfed4b24b
ad_axi_ip_constr.xdc: Delete file
2017-03-30 16:16:02 +03:00
8ba6012b6b
restructure: Move xilinx specific constraints to /library/xilinx/common/
2017-03-30 16:16:02 +03:00
335fef0f42
ad_axi_ip_constr: Split up this constraint file into separate files
...
For experimentation, to solve a constraint scoping issue, split up the
ad_axi_ip_constraint file into separate constraints file, in function
of there parent module.
2017-03-29 18:31:40 +03:00
b0e88eb5ff
axi_ad9361- add receive init delay
2017-03-13 16:28:24 -04:00
1d6ddacfd6
axi_ip_constr: Fix constraints
...
The filter for CDC registers were too generic, and a few non-CDC
register were set as asynchronous register.
2017-02-27 16:25:09 +02:00
2da7dd4079
axi_ip_constr: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-23 11:33:25 +02:00
db924953bb
altera- warnings about init values
2017-01-30 10:01:28 -05:00
3f3a8bd267
library: forced ad_mem module to be implemented in BRAM for Xilinx devices
2017-01-25 18:12:04 +02:00
c0a2ef1ac4
library- altera power up warnings
2016-12-20 16:18:15 -05:00
ce47cf8d30
ad_sysref_gen: Fix sysref generation
...
Toggle sysref output just if the sysref_en is asserted.
2016-12-19 18:02:49 +02:00
a228c05bd3
common: Add a SYSREF generation module
...
The SYSREF generator is using a simple free running counter,
which runs on the JESD204 core clock. The period can be
configured using a parameter, it must respect the constraints
defined by the JESD204 standard.
The generator can be enabled through a GPIO line.
2016-12-17 11:12:10 +02:00
a00d9870be
axi_ip_constr: Fix constraints
...
Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
2016-12-16 12:01:38 +00:00
12d6e46ae7
clean: Delete deprecated source files
...
The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located
at library/xilinx and library/altera.
The axi_jesd_xcvr was an early version of axi_adxcvr.
The register map is moved to the IP's directory.
2016-11-14 10:43:46 +02:00
5eff357568
up_tdd_cntrl: Fix memory map register writes
2016-11-01 10:06:57 +02:00
8e25bc01b3
all: Change tab to double space
...
Occasional file parsing and restructuring become a pain, if tabs exists
in code. General rule of the repos is tab always a double space.
2016-10-01 18:13:42 +03:00
6735333aea
common- dac data path split
2016-09-23 16:13:24 -04:00
8729af1b91
common- adc- data path disable split
2016-09-23 13:40:35 -04:00
78f7384150
ad9361- vivado synthesis warnings fix
2016-09-22 13:41:18 -04:00
2b6eb1d65e
up_drp: Revert some bit locations
...
Linuxe drivers are checking the drp_locked status even if the
core does not contains a clock generation/managment module. To
not break all the designs, revert all the status and control bits to
there old locations.
2016-09-22 16:32:42 +03:00
a21b9fe8ff
up_drp: Fix up_drp_wr
2016-09-21 17:55:58 +03:00
913eafed48
up_drp : Update the DRP interface to support Altera platforms
2016-09-21 15:00:45 +03:00
10408b8c88
up_tdd_cntrl: Set PCORE version to 1.00.a
2016-09-21 10:27:28 +03:00
74bc498a6d
library/common- added dac clock select
2016-08-26 10:31:00 -04:00
e754f0a46a
up_axi- writes dropped by delayed w-responses
2016-08-14 11:21:19 -04:00
1d33d7d7ee
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
2016-08-08 15:07:42 +03:00
90ac7b7ac9
lib_refactoring: Move all Altera module to library/altera/common
...
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
b806fa3b42
lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
2016-08-08 15:06:10 +03:00
b99117e686
up_axi: Same cycle BVALID/READY fails on Altera
...
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.
Similar to:
2817ccdb22
2016-08-01 12:17:10 +03:00
58b220ba81
ad_tdd_control: Add an on/off switch to the receive datapath
...
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
8a2734b43e
up_dac_common- typo- unf register reset
2016-07-28 13:44:57 -04:00
db6d5f509f
library/common- xcvr interface logic
2016-07-21 16:09:33 -04:00
ced36f6159
up-dac- support iq mode
2016-07-21 11:58:03 -04:00
040f72d172
ad_mul_u16: Delete unused module
2016-07-20 14:17:04 +03:00
2dd6bb0cb8
up_drp_cntrl: Delete unused module
2016-07-20 14:17:04 +03:00
af9915b060
up_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
df43ca9332
ad_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
64633e519c
Merge remote-tracking branch 'origin/dev_ad7616' into dev
2016-06-29 12:32:39 +03:00
aee38e1cc9
up_hdmi_tx: Fixed data path width
2016-06-14 14:27:03 +03:00
9d1ae436b1
common/util_pulse_gen: Rename the ad_tdd_sync module
2016-06-09 10:07:47 +03:00
f10c1e6e93
axi_hdmi_tx: Remove hdmi_full_range register
2016-05-27 14:04:40 +03:00
6bc05fc844
ad_*_in: register post-iob
2016-05-16 12:19:38 -04:00
cd7c9c99ed
ad_*_clk: altera-pll not supported by qsys flow
2016-05-16 12:19:38 -04:00
9cd6e2da51
quartus-mess- altddio direct instantiation
2016-05-09 13:54:08 -04:00
726ddb6e93
ad_lvds_clk: Fixed assignment mismatched
2016-05-09 10:32:18 +03:00
b36c722ec9
up_hdmi_tx: Discard the standard default values
...
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
2016-05-05 13:41:46 +03:00
d82ca5dc3c
library/common- altera variations
2016-05-04 13:42:11 -04:00
89f5d2394e
altera- clock variations
2016-04-29 10:17:35 -04:00
3563c2212c
common/altera- removed dcfilt/mul
2016-04-29 10:17:35 -04:00
0260280db1
common/altera- data path
2016-04-29 10:17:35 -04:00
ed62101308
common/altera: primitives
2016-04-29 10:17:35 -04:00
ad227c1af0
up_axi: Wait more to a valid read acknowledge.
2016-04-25 10:34:17 +03:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
42cd05ab19
ad_mem_asym: Add support for more ratios.
...
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
6fe41ebb08
axi_hdmi_tx: Upgrade hdmi clipping process
...
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
65b2e51958
common/mmcm: add another clock
2016-03-22 12:50:59 -04:00
7a320a3d34
ad_lvds* - updates
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
a8e9d72273
adc/dac - prefix parameters
2016-02-17 14:16:04 -05:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
d1e638349b
ad_serdes_clk : The reference clock selection line should by tied to 1
...
Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
29a0f27cd1
ad_edge_detect: Add a flop to output, reset is active high
2015-12-14 15:40:29 +02:00
12c95b059d
ad_tdd_control: Remove tdd_enable_synced control line
...
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
5cf45b2978
axi_clkgen: Added phase related parameters
2015-12-02 18:50:23 +02:00
667e49fe41
library: Axi_clkgen, added register for controlling the source clock.
...
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
593c486168
ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received
2015-11-24 15:15:53 +02:00
c70be7391f
ad_tdd_control: Avoid unnecessary reset on control lines
...
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
985f2ca020
library: ad_rst, added comment so that the registers are not minimized away
2015-11-24 10:33:38 +02:00
9ba8c059ce
ad_tdd_sync: Fix reset value of the pulse_counter
2015-11-13 18:31:24 +02:00
d6eae81bc1
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 18:14:21 +02:00
3c27b3a4c5
ad_lvds_in: Add single ended option
2015-11-13 12:13:09 +02:00
b17fec689e
ad_tdd_control: An active sync pulse can NOT be a reset for the control lines
...
By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
2015-11-11 11:13:33 +02:00
fc0f4bc414
axi_ad9361: Delete the old sync generator from the core
...
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
e7fd964874
axi_clkgen: Added a second input clock option
2015-11-06 17:55:29 +02:00
6cfc13a9dd
common: Allow for the memory to be also symetrical
2015-11-04 13:28:02 +02:00
f1ed27105f
library/common- reset fix
2015-10-23 14:32:35 -04:00
8ecdb4a4ca
library/tdd_control: Add common registers to the register map and fix init value of a register
...
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
96d363849e
ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block
2015-10-09 13:43:14 +03:00
5c3f90a676
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
97a9ecfc9a
axi_hdmi_rx: Update constraint file and fix reset line
2015-09-29 18:49:30 +03:00
b765be568f
up_gt_channel: Delete the register, which stores transceiver type
...
Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
cffb2e6226
up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address
2015-09-29 14:19:52 +03:00
a0ac0e912b
up/ad_gt_common/channel: Cosmetic changes
2015-09-29 14:16:24 +03:00
c03983ca54
ad_tdd_sync/control: Update TDD logic
...
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
884f45c81d
common library: Registered dc_filter and iq_correction coefficients
2015-09-16 14:24:18 +03:00
5bc16159fa
ad_tdd_sync: The resync will reset all the control lines
2015-09-10 11:28:36 +03:00
85ffc25ec5
ad_tdd_sync: Update the synchronization logic
...
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
5a566b9e5d
ad_tdd_control: Add delay compensation for the control lines
2015-09-09 12:24:26 +03:00
1cd3435147
up_delay_cntrl- cosmetics
2015-08-28 13:16:18 -04:00
8fddf983d2
up_hdmi_tx- common/generic instance names
2015-08-27 13:17:06 -04:00
20ee10ea46
common/ad_lvds_out- add single ended
2015-08-27 11:41:47 -04:00
ba64de228e
ip-constr- register name changes
2015-08-27 11:18:00 -04:00
0077117f94
dac/adc- make common instances
2015-08-21 14:41:39 -04:00
c45d39df51
dac/adc- make common instances
2015-08-21 14:41:35 -04:00
e3ec6b48fc
dac/adc- make common instances
2015-08-21 14:41:30 -04:00
f31c1c9caa
dac/adc- make common instances
2015-08-21 14:41:26 -04:00
e4e4700950
dac/adc- make common instances
2015-08-21 14:41:13 -04:00
54b4365f6c
dac/adc- make common instances
2015-08-21 14:41:09 -04:00
799001403f
mult-macro: use primitive parameters
2015-08-20 13:54:16 -04:00
b0079e60bf
ad-rst - common instance for adc/dac
2015-08-20 11:37:16 -04:00
6ae0c8f85e
library: Fixed changes related to parameters
2015-08-20 18:13:54 +03:00
928ee4972b
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:43 -04:00
483e375910
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:38 -04:00
f8b3346e97
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
041be729f6
common/ip-constrs- uniform simple constraints will do
2015-08-13 13:03:51 -04:00
a2b816beda
common/up_hdmi_tx: wrong clock on vdma status signals
2015-08-13 13:03:51 -04:00
5edf61c40a
ad_rst:- allow preset to be synchronized as reset
2015-08-13 13:03:51 -04:00
2bcac36e33
common/up_- change to asynchronous resets
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
e4f94664a6
axi_jesd_gt- remove per lane control/status to channel
2015-08-13 13:03:51 -04:00
f807490ed1
axi_jesd_gt- per lane group
2015-08-13 13:03:51 -04:00
4c8206608c
axi_jesd_gt- separate es-axi
2015-08-13 13:03:51 -04:00
e4b0710923
axi_jesd_gt- per lane split-up
2015-08-13 13:03:51 -04:00
ad80561379
TDD_regmap: Fix CDC for control signals
2015-08-06 15:16:39 +03:00
e19d476b58
TDD_regmap: Fix addresses
2015-08-06 15:15:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
cd5ce3349f
iqcor- move i/q sel inside the module
2015-07-23 15:55:45 -04:00
a4461545fa
axi-ip: constraints - altera
2015-07-22 12:46:06 -04:00
559893c0a3
altera- obsolete cores
2015-07-21 11:04:26 -04:00
86dabbe5fc
jesd-align-- xilinx/altera merge
2015-07-21 10:57:00 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
6e3817d419
axi_jesd_xcvr: individual reset control
2015-07-13 10:04:34 -04:00
b25b2e3020
registers for signal tap
2015-07-08 15:47:45 -04:00
ea2bd71904
synchronize up signals separately
2015-07-07 12:51:13 -04:00
c1fcbeec8e
library/axi_jesd_xcvr: interface name matching
2015-07-07 10:21:53 -04:00
3a5da47239
xcvr- initial checkin
2015-07-06 13:51:55 -04:00
cf6052e2a8
axi_hdmi_tx: Add control to bypass chroma sub-sampler
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Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
d6c64e031f
axi_hdmi_rx: Drop TPG enable from register map
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The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
542d64bb5a
up_hdmi_rx: Fix enable control
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Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
231a21548c
up_hdmi_rx: Fix TPM OOS clear
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The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
185e489802
cpack- signaltap mess
2015-06-29 16:31:53 -04:00
6862655b0d
Add .gitattributes file
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Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
ac6e28c461
library/common: add altera signaltap
2015-06-19 14:33:01 -04:00
Adrian Costina
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Istvan Csomortani
Dragos Bogdan
Matthew Fornero
Shrutika Redkar
AndreiGrozav