Commit Graph

8 Commits (79e21a361ce8e763ab931ca5b215cc130ed33773)

Author SHA1 Message Date
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 6d4430cfda axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access
When using non-broadcast access to the GT DRP registers lane filtering is
done on both sides. The ready and data signals are filtered in the in the
axi_adxcvr module and the enable signal is filtered in the util_adxcvr
module. This works fine as long as both sides use the same transceiver IDs.
E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the
util_adxcvr module.

But this is not always the case. E.g. on the ADRV9371 platform there are
two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr.
The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses
lane 2 and 3.

Non-broadcast access for the first RX axi_adxcvr module works fine, but
always generates a timeout for the second axi_adxcvr module. This is
because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the
util_adxcvr and when ID based filtering is done both can't match at the
same time.

To avoid this perform the filtering for all the signals in the axi_adxcvr
module. This makes sure that the same base ID is used.

This also removes the sel signal from the transceiver interfaces since it
is no longer used on the util_adxcvr side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 17:30:51 +02:00
Lars-Peter Clausen d883aabcc1 adi_ip.tcl: Use analog.com for interface vendor
Currently the scripts use 'analog.com' as the vendor property for IP cores,
but 'ADI' for interfaces.

Make things consistent by using 'analog.com' for both interfaces as well
as IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:10:15 +02:00
Rejeesh Kutty 1e54b5230f axi_adxcvr- add m_axi associated clock 2017-02-02 11:17:56 -05:00
Istvan Csomortani d3ed417f49 axi_adxcvr: Update the packaging script to fix infer mm issues
- Change the clock and reset port name of the AXI slave interface
to s_axi_aclk and s_axi_aresetn. This way we can use the adi_ip_properties
process to infer the interface.
  - Define an address space reference to the m_axi interface.
2017-01-19 15:16:04 +02:00
Rejeesh Kutty c57ffc9364 axi_adxcvr- separate pll reset from channels 2016-11-22 11:12:54 -05:00
Shrutika Redkar 829e4155ca modified transceiver configuration files 2016-08-10 14:59:38 -04:00
Rejeesh Kutty 2b7c976be5 xcvr- altera/xilinx split 2016-08-04 13:26:10 -04:00