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3 Commits (7a6ce70e1904eff8ec6653af40d01ee8afb4b8f9)

Author SHA1 Message Date
Lars-Peter Clausen 8326022adc axi_dmac: address_generator: Fix disable race condition 
If the address generator is disabled the very same cycle as it tries to put a
new address on the bus, it will keep sending this address forever and the core
will lock up

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-07 18:40:49 +01:00
Lars-Peter Clausen 6da9c65a08 axi_dmac: Add support for zero latency transfer switching 
Right now there is always a period of one clock cycle where we can not transfer
any data when switching between two transfers. This patch modifies the data
mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-07 18:39:20 +01:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00