3ab0f417b4
util_dac_unpack: Don't use localparam symbols in input/output signals
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When using a localparam for the width of a input/output signal the tools
won't be able to infer the size of the signal. This results in the signal
always being only 1 bit wide which causes the design to not work.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:19 +03:00
04e4458ee1
util_dac_unpack: Drive unused ports to 0
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Silences a few warnings about undriven ports from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:12 +03:00
43e9b0c7a6
common: Disable TTC0 MMIO routing for PS7
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We do not use the ttc0 to MMIO routing, but it is enabled by default, so
explicitly disable it.
2014-10-10 16:19:51 +03:00
61be003017
axi_i2s/axi_spdif: Create clock and reset interface for DMA bus
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This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:41 +03:00
58cbe1813d
scripts/adi_ip: Add helper function to create bus clock and reset interface
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Add a helper function that can be used to register a clock and a reset interface for the clock and reset signals of a bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:31 +03:00
a31cb6c475
axi_i2s/axi_spdif: Remove manual creation of Streaming AXI bus
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It looks like Vivado is now able to infer these buses from the sources.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:06 +03:00
e361bbbd04
Revert "fmcomms2_udc: Initial check in"
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This reverts commit ddc7c845e9
2014-10-10 14:48:55 +03:00
7659f3438c
AD9467: Fixup swapped net names
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Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-10-10 12:33:07 +03:00
adf4893a27
usdrx1: remove constraints and other changes
2014-10-09 15:25:08 -04:00
4bdb3cd262
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:07 -04:00
6125bbecc3
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:06 -04:00
2817ccdb22
up_axi: altera can not handle same clock assertion of arready and rvalid
2014-10-09 15:25:05 -04:00
ddc7c845e9
fmcomms2_udc: Initial check in
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FMCOMMS2 with an additional SPI port for the up/down converter board
2014-10-09 19:01:22 +03:00
6f77af4aff
fmcjesdadc1: Upgrade project to 2014.2
2014-10-09 18:55:27 +03:00
2da395926e
fmcomms2: Upgrade project to 2014.2
2014-10-09 18:54:33 +03:00
4f6aa159b8
mitx045: Base design now support 2014.2
2014-10-09 15:11:28 +03:00
edeeafa47d
ad9671_fmc: Added sof information to the AD9671 driver
2014-10-09 14:52:25 +03:00
072e11c661
ad9467_fmc: Upgrade the axi_quad_spi core
2014-10-08 15:22:58 +03:00
fc38249150
ad9467 ZED: Fix over range signal path, and the dma interface.
2014-10-08 11:24:44 +03:00
15db557bd6
ad9467 ZED: Cosmetic changes on bd script.
2014-10-08 11:24:32 +03:00
5565cf8fad
axi_ad9467: Independent read/write update
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Independent read/write operation is supported on "up" interface
2014-10-08 11:23:44 +03:00
82717b354a
ad9467_fmc : Upgrade project to 2014.2
2014-10-08 11:21:43 +03:00
b2d0260130
ad9467_fmc: Prevent to use concatenation module on SPI interface
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This module cause unnecessary issues during version upgrades.
2014-10-08 11:20:45 +03:00
88a3b7f8fd
library: remove all constraints for now
2014-10-07 16:59:19 -04:00
27153fff41
ad9625x2_fmc: updated to 2014.2
2014-10-07 16:05:09 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
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axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
95842b8949
ad9434_fmc: Fix adc_valid signal path
2014-10-07 18:02:33 +03:00
a436153a48
axi_ad9434: Independent read/write update
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Independent read/write is supported on "up" interface.
2014-10-07 18:01:44 +03:00
115f33b8d6
ad9434_fmc: Fix pin constraints for ZC706
2014-10-07 17:58:29 +03:00
9404e93126
ad9434_fmc: Fix PN monitor.
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No need to flop the incoming data.
2014-10-07 17:56:27 +03:00
c1213ffe71
ad9434_fmc: Fix SPI interface
2014-10-07 17:51:14 +03:00
66baf6ac3e
axi_ad9434: Deleted unused ip file
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ad_lvds_in.v is not used in this ip core.
2014-10-07 17:47:08 +03:00
bfa17844ff
ad_serdes_in: General update
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Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
151781a2af
axi_ad9467: Fix PN sequence checker
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Make sure that the reference PN sequence is only incremented every two clock
cycles to make sure that it matches the rate of the ADC PN sequence.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-07 16:26:53 +03:00
59640f181b
ad9467: Fix LVDS delay interface.
2014-10-07 16:25:22 +03:00
cd42345324
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
bca8ec0160
daq2: 2014.2 and ver.d
2014-10-06 14:56:01 -04:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
d47776a4a0
ad9152: 9144 copy
2014-10-06 10:34:01 -04:00
525373fc04
daq3: daq2 copy
2014-10-06 10:34:00 -04:00
210da4116f
scripts: initial commit
2014-10-03 16:13:34 -04:00
581892b22a
axi_ad9265: Updated project with new up independent read/write
2014-10-03 12:32:08 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
89964be59e
fmcomms1: Updated project to vivado 2014.2
2014-09-30 10:32:18 +03:00
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
3c25c1171d
fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms
2014-09-26 10:28:07 -04:00
87c4c73e22
ad9434: Fix adc_clk constraint
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ADC clock is 500 Mhz.
2014-09-25 16:54:06 +03:00
82ed885b53
ad9434: Fix SPI line physical constraints
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SPI lines are not differential.
2014-09-25 16:53:16 +03:00
Lars-Peter Clausen
Istvan Csomortani
Paul Cercueil
Rejeesh Kutty
Adrian Costina
Michael Hennerich