2 Commits (7b3d52436a93d8a7da1094459920261d58273fef)

Author	SHA1	Message	Date
Laszlo Nagy	4b13274c55	ad9361/all/system_constr.xdc: remove manual clock definition ... Having a clock assigned manually to the clk output pin of the axi_ad9361 let the Vivado timing engine to not ignore the clock insertion delay when analyzing paths between clk_0 and the manually created clock that has the same source (clk_0), resulting in timing failure.	2019-04-12 10:48:50 +03:00
Istvan Csomortani	9ecfcce4ec	adrv9364z7020: Rename pzsdr1 to adrv9364z7020	2017-05-25 17:20:23 +03:00