Commit Graph

30 Commits (7b3d52436a93d8a7da1094459920261d58273fef)

Author SHA1 Message Date
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Laszlo Nagy e22016de4c adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters
Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
2019-10-08 10:38:46 +03:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
AndreiGrozav 44deaadb4a adrv9371: Add decimation and interpolation filters 2019-08-20 16:24:47 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
Laszlo Nagy b98eb28dca adrv9371: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy e864786d3a adrv9371: use generic TPL
Use the generic TPLs for a better scalability to ease lane number
reductions.
2019-01-14 17:21:00 +02:00
Lars-Peter Clausen aed8478d10 adrv9371x: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Istvan Csomortani 15863795e8 adrv9371x:kcu105: Performance_Retiming results the highest WNS
In default strategy we having a few path with small negative slack inside of
the MIG, due to the high UI clock (300MHz).

This new strategy solves this issue.
2018-08-23 18:41:48 +03:00
Istvan Csomortani 2293374307 adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs
The affected projects are:
  - FMCADC2/VC707 - 16Mb
  - FMCADC5/VC707 - 16Mb
  - DAQ2/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ2/KC705  - ADC@4Mb and DAC@4Mb
  - DAQ2/VC707  - ADC@8Mb and DAC@8Mb
  - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
  - DAQ3/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
  - ADRV9371x/KCU105 - DAC@8Mb
  - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-21 11:44:05 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 9a44ab921b adrv9371: Swap CSN lines to preserve consistency 2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
AndreiGrozav 502989c25f jesd_rst_gen:constraints: Remove invalid false path definitions
The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
AndreiGrozav 8403ff17ec adrv9371x/kcu105: Use ultrascale type primitives in axi_clkgen IP 2018-02-13 17:33:38 +02:00
AndreiGrozav 2302d3516d adrv9371x:kcu105: Update transceiver configuration 2018-02-13 17:33:38 +02:00
Adrian Costina 73ef0fb48c adrv9371x: kcu105: Fix transceiver and clock placement 2018-02-13 17:33:38 +02:00
Michael Hennerich 2e59a70cdd adrv9371: Increase FCLK2 to 200MHz to support max sampling rates
This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2018-01-09 15:20:06 +01:00
Lars-Peter Clausen 46acdadb92 adrv9371x: Set correct transceiver type for UltraScale projects
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.

This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.

It is also necessary for correct eye scan support in the axi_adxcvr block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
Istvan Csomortani 700ed156ab [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx 2017-09-25 08:56:40 +01:00
AndreiGrozav c0da4e6192 adrv9371x_kcu105: Initial commit 2017-08-22 15:41:49 +03:00