Commit Graph

61 Commits (7be66b63c1f5533234395f39462164c14e70e3d3)

Author SHA1 Message Date
AndreiGrozav 3d407a3ba5 axi_ad9467: Fix missing connection warnings 2020-09-11 10:24:22 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 20b0c92a1f iodelay: Expose the REFCLK_FREQUENCY parameter 2019-06-11 18:13:06 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
AndreiGrozav 7dcaaea04e library: Update scripts/adi_ad_ip.tcl and IPs
Fix library makefiles dep list using generic vendor info reg

Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
2019-04-09 16:07:14 +03:00
AndreiGrozav 4ae5a6d3d8 library/IPs: Auto-generate bd.tcl Update
Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:

  - axi_ad5766/axi_ad5766_ip.tcl
  - axi_ad6676/axi_ad6676_ip.tcl
  - axi_ad9122/axi_ad9122_ip.tcl
  - axi_ad9144/axi_ad9144_ip.tcl
  - axi_ad9152/axi_ad9152_ip.tcl
  - axi_ad9162/axi_ad9162_ip.tcl
  - axi_ad9250/axi_ad9250_ip.tcl
  - axi_ad9265/axi_ad9265_ip.tcl
  - axi_ad9361/axi_ad9361_ip.tcl
  - axi_ad9371/axi_ad9371_ip.tcl
  - axi_ad9434/axi_ad9434_ip.tcl
  - axi_ad9467/axi_ad9467_ip.tcl
  - axi_ad9625/axi_ad9625_ip.tcl
  - axi_ad9671/axi_ad9671_ip.tcl
  - axi_ad9680/axi_ad9680_ip.tcl
  - axi_ad9684/axi_ad9684_ip.tcl
  - axi_ad9739a/axi_ad9739a_ip.tcl
  - axi_ad9963/axi_ad9963_ip.tcl
  - axi_adrv9009/axi_adrv9009_ip.tcl
  - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
  - axi_hdmi_tx/axi_hdmi_tx_ip.tcl
  - xilinx/axi_adxcvr/Makefile
  - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
  - xilinx/util_adxcvr/Makefile
  - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-30 11:26:11 +02:00
AndreiGrozav ceb08feee2 Add license header on tcl files 2019-03-30 11:26:11 +02:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
Lars-Peter Clausen 324da5f112 Remove unused DMA underflow signal from ADC DMA interface
The ADC DMA will never underflow and unsurprisingly the adc_dunf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 17:21:20 +02:00
Lars-Peter Clausen 5b58fb67f0 library: Remove empty constraint files
Most of the cores are fully covered by the generic constraint files. When
the constraints where moved from the core specific to the generic
constraint files some empty core constraints files where left around. These
don't do anything, so remove them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 2b914d33c1 Move Altera IP core dependency tracking to library Makefiles
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.

For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.

Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.

Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.

This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 35a39ba2e6 Regenerate library Makefiles using the new shared Makefile include
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Adrian Costina 493fc1d48b axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
A couple of new parameters and new ports are missing in several
up_[adc|dac]_[common|channel] instance, and generates warnings. The rule of
thumb is to use full instantiations, defining all the existing parameter and
ports of the module.

Fix all the instantiation of up_[adc|dac]_[common|channel], by defining all its
parameters and ports.
2018-04-11 15:09:54 +03:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen de4fe30238 library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
The external s_axi_{awaddr,araddr} signals that are connect to the core
have their width set according to the specified size of the register map.

If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently
is for many cores) the MSBs of those signals are left unconnected, which
generates a warning.

To avoid this make sure that the signal width matches the declared register
map size.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:25 +02:00
Rejeesh Kutty 0aafd049c9 hdlmake.pl- remove ad_lvds 2017-07-26 10:32:44 -04:00
Rejeesh Kutty 893af8d3e6 library & projects- ad_lvds/ad_data replace 2017-07-26 10:31:48 -04:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
AndreiGrozav e4ae391237 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
Rejeesh Kutty fea6eb68be up_adc_common- port name changes 2017-05-10 14:45:17 -04:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
2017-03-30 16:16:02 +03:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Rejeesh Kutty 6837143110 library/ adc parameter changes 2016-09-23 13:44:47 -04:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Shrutika Redkar 6ebb32a194 library axi-slave missing protection signal added 2016-07-22 12:54:27 -04:00
Rejeesh Kutty c293c04634 hdl make updates 2016-06-01 13:53:09 -04:00
Rejeesh Kutty 1aac44b0d9 library: ad_*clk- rst/locked 2016-05-04 13:42:11 -04:00
Istvan Csomortani 07e2d281c0 Make: Update Make files 2015-09-25 19:11:21 +03:00
Istvan Csomortani aa608e3907 axi_ad9467: Update constraints 2015-09-23 14:26:57 +03:00
Istvan Csomortani 7b858bc5ad Revert commit 6b99ce
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
Adrian Costina 6b99ce2482 library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2 2015-08-20 18:17:38 +03:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Istvan Csomortani 46fa91d5be Makefile: Update Make files 2015-07-03 18:08:57 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Adrian Costina 8a1f4bf5f6 ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports 2015-06-09 14:21:12 +03:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Rejeesh Kutty 297e885981 library- drp moved to up-clock domain 2015-06-01 14:52:52 -04:00
Rejeesh Kutty e918588a4b library: remove axi-min-size parameter 2015-05-19 13:07:48 -04:00
Rejeesh Kutty f53204f9f9 ad9467: delay changes 2015-05-19 12:53:56 -04:00
Adrian Costina a61a195e3f Makefiles: Updated makefiles to add the new constraints as dependecies 2015-04-23 11:16:39 +03:00
Adrian Costina b4a09daf89 axi_ad9467: Added CDC and reset constraints 2015-04-23 10:30:33 +03:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00