The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.
Projects which use spi_engine.tcl will be updated to account for
these changes.
If the sampling clock is lower than dclk*number_of_active_lines*32 the interface should wait for the next adc_ready signal to reset the counter.
The adc_valid_p signal should be set high just for a clock period after the sample was captured.
- Issue introduced by commit 173f4a83d4
- When IODELAY_ENABLE was inserted in axi_adrv9001_if for adrv9001_rx (Xilinx instance),
for Intel instance (intel/adrv9001_rx.v) was omitted and caused a build error for
adrv9001/a10soc
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Replaced the existing axi_tdd with the new version
* Added DEFAULT_POLARITY synth parameter and RO register
* Added TDD_STATUS register
* Added TDD_SYNC_RST feature
* Used the asy_ prefix for signals which are not synced
* Added logic to force the state from ARMED to RUNNING when startup_delay=0
* Added feature to finish the burst when the module is disabled before its completion
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
New improvements for the ADI DMAC IP:
1)The capability to manually overwrite the DMA_AXI_ADDR_WIDTH(from GUI or from tcl)
2)DMA_AXI_ADDR_WIDTH attribute is now visible in the Vivado GUI:
-"Auto mode": Automatically calculated by the core tcl files based on the existing attached address segments.
-"Manual mode": Specify the desired dma_width between 32-64 bits.
3)Added two new debug registers that return higher part of the current source/destination address.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
If 'xvlog' or 'xelab' xilinx commands are failing, exit from
run_tb.sh script without trying to run simulation.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
Update clean command to delete also files generated by simulation,
from 'tb' folders, covering cases for Xsim and ModelSim simulators.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
* Before, adc_valid was for the previous sample. This said that
at the second rising edge of clk_gate - the first sample is valid,
which is not true
* Alongside with the software issue that will be solved, these fixes
will make the first 2 samples to be with valid data, otherwise the
user has to always keep in mind that the first 2 ones are invalid
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.
* library/axi_ad777x: Initial commit for Xilinx and Intel
* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
When capture length is not programmed the DMA will interrupt the
transfer once it received all the samples he was set in its descriptor,
this case must be handled by resetting the read process and returning
an end of transfer (eot) to the data offload control logic.
Tx path was gated by the FSM also in bypass mode. This must be avoided
since the bypass mode should be independent of the FSM.
Write to bypass fifo only when bypass is enabled
alin724
AndreiGrozav
laurent-19
Sergiu Arpadi
PopPaul2021
Jem Geronimo
Istvan-Zsolt Szekely
Iulia Moldovan
Filip Gherman
Ionut Podgoreanu
stefan.raus
PopPaul2021
Laszlo Nagy
LIacob106