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42 Commits (7da98277821dff950871b3a8cafa6b2b789da7ed)

Author SHA1 Message Date
Ionut Podgoreanu 5b95b6ce1f ad9081_fmca_ebz: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
Laszlo Nagy e332409610 ad9081_fmca_ebz: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Ionut Podgoreanu 5a06f186ae ad9081_fmca_ebz/common: Use the script to compute the TPL width 2022-08-25 12:35:42 +03:00
Laszlo Nagy d48b1bcdce ad9081_fmca_ebz/vck190: Expose ref clock parameter 2022-08-04 09:52:57 +03:00
Laszlo Nagy 78333b2c90 ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx 2022-08-04 09:52:57 +03:00
Laszlo Nagy 2b274f945f ad9081_fmca_ebz: Reset cpack with Rx data offload 2022-08-01 12:47:26 +03:00
Laszlo Nagy dbadb9eb61 ad9081_fmca_ebz/common: Make data offload memory type selectable 
Make the storage type over writable so it can be set specifically
to carriers.

Address width of external memory AXI master is calculated in the
interfacing core (util_hbm) so that parameters is removed.
 2022-04-28 14:31:32 +03:00
David Winter 638491d502 projects: ad9081: Disable tdd_sync CDC sync of TDD controller 
Signed-off-by: David Winter <david.winter@analog.com>
 2022-04-20 10:54:53 +03:00
Laszlo Nagy 45dae0f3d3 ad9081_fmca_ebz/common: Connect sync at TPL level 
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
 2022-02-07 19:14:01 +02:00
Laszlo Nagy 80b3fc2d0a ad9081_fmca_ebz: versal: Remove unused GT reset input pin 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-22 16:18:29 +02:00
Laszlo Nagy e00def31d0 ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
Laszlo Nagy 0b9631f1f7 ad9081_fmca_ebz: versal: Rename nets 2021-11-19 14:01:48 +02:00
Laszlo Nagy ca6248ba88 ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL 2021-11-19 14:01:48 +02:00
Laszlo Nagy 731ed0a7a5 ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver 
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.

Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-19 14:01:48 +02:00
Laszlo Nagy 1d951cfbae ad9081_fmca_ebz/vck190: Change default profile to 2 lanes 2021-11-19 14:01:48 +02:00
stefan.raus adad6c930d ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters 
For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
 2021-11-12 13:04:57 +02:00
Laszlo Nagy 3a1babe366 ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock 
Reset transceiver with a pulse
 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2562aead32 ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6c58a8d1ab ad9081_fmca_ebz/common: Add Versal transceiver support 2021-10-05 14:09:51 +03:00
David Winter edd2956d58 data_offload: Fix util_[cu]pack offset to TDD syncs 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-30 14:45:54 +03:00
David Winter b9554a9a5a ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-09-30 14:45:54 +03:00
David Winter e9e278c898 ad9081_fmca_ebz: Remove bypass gpio 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 2178191610 ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine 
Memory requirements are the same as with the dacfifo (1 MiB).

Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
Laszlo Nagy cf7f45ffcc ad9081_fmca_ebz: Fix for F=8 2021-05-14 15:39:40 +03:00
Laszlo Nagy 680d28476c ad9081_fmca_ebz: Add LANE_RATE param to all projects 
The block design expects a lane rate to be set in the system project.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 693c002668 ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR 
Remove Xilinx PHY and simplify project
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d92f925b06 ad9081_fmca_ebz: Disable XBAR from DAC TPL 2021-05-14 15:39:40 +03:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0 
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
 2021-03-08 11:29:33 +02:00
Laszlo Nagy 6b13b32f24 ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size 2021-03-04 11:13:29 +02:00
Laszlo Nagy ddd8a14790 ad9081_fmca_ebz: Remove system reset from Xilinx PHY 
Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
 2021-02-05 15:24:15 +02:00
Laszlo Nagy af3e1c7003 ad9081_fmca_ebz/a10soc: Np 12 support 2021-02-05 15:24:15 +02:00
Laszlo Nagy d0f8a81b2f ad9081_fmca_ebz: Np 12 support 
204B functional
204C functional
 2021-02-05 15:24:15 +02:00
Laszlo Nagy 0fd5590e56 ad9081_fmca_ebz: a10soc: Initial version 
Parametrizable project with default profile of:

  M=8 L=4 SampleRate=250 MSPS
  LaneRate=10 Gbps
 2021-02-05 10:24:59 +02:00
Laszlo Nagy 3dd370a27c ad9081_fmca_ebz: enable xbar in DAC TPL 2020-11-27 09:45:11 +02:00
Laszlo Nagy e9f319e3d7 ad9081_fmca_ebz: HP0 is already initialized in ZC706 
On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
 2020-11-12 15:46:27 +02:00
Laszlo Nagy e8f6523197 ad9081_fmca_ebz: adapt to renamed tpl core 2020-05-20 19:08:25 +03:00
Laszlo Nagy cbb23c7b67 ad9081_fmca_ebz: fix Xilinx PHY resets 
Avoid clock domain crossing on resets.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy e112a03d85 ad9081_fmca_ebz: Whitespace cleanup 
Clear extra lines and whitespaces at end of lines.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy 7df4caf8b0 ad9081_fmca_ebz: Added parameter description 
Add parameter description to project and common block design file
 2020-04-23 17:21:05 +03:00
Laszlo Nagy e433d3f808 ad9081_fmca_ebz: expose PLL selection as a parameter 
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
  0 - CPLL
  1 - QPLL0
  2 - QPLL1

Since the selection of line rate is available from the project also the
PLL selection must be exposed.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy b774e1ca7d ad9081_fmca_ebz: enable IQ rotation 2020-04-03 11:16:37 +03:00
Laszlo Nagy f3630dd95b ad9081_fmca_ebz: common block design 
Parametrizable block design with selectable JESD physical layer between
Xilinx Phy and ad_utilxcvr.
 2020-03-10 18:19:03 +02:00