* Removed empty/commented lines * Regenerated Makefiles * Removed redundancies adc channels data width * Set data width 32-bit: max resolution and CRC header Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
* Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
Because the inferface signals which pass through the eval board's Arduino connector are connected to level shifters the design will not work at the maximum clk frequency of 48MHz. The maximum tested frequency is 24MHz.
laurent-19
PopPaul2021
sergiu arpadi