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5 Commits (7da98277821dff950871b3a8cafa6b2b789da7ed)

Author SHA1 Message Date
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters. 
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2022-11-14 09:38:42 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Lars-Peter Clausen 6d31a437aa dac_fmc_ebz: Add initial Arria10 SoC support 
Add support for the Arria 10 SoC development kit to the dac_fmc_ebz
project.

This allows to use the following FMC boards on the Arria 10 SoC development
Kit carrier:
  * AD9135-FMC-EBZ
  * AD9136-FMC-EBZ
  * AD9144-FMC-EBZ
  * AD9152-FMC-EBZ
  * AD9154-FMC-EBZ
  * AD9171-FMC-EBZ
  * AD9172-FMC-EBZ
  * AD9173-FMC-EBZ

Note that the board in its default configuration is not fully compatible with the
mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is
required. The rework concerns the LA01 and LA05 pins, which by default are
not connected to the FPGA. The changes required are:

  LA01_P_CC
    R612: R0 -> DNI
    R610: DNI -> R0
  LA01_N_CC
    R613: R0 -> DNI
    R611: DNI -> R0
  LA05_P
    R621: R0 -> DNI
    R620: DNI -> R0
  LA05_N
    R633: R0 -> DNI
    R632: DNI -> R0

The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are:
  * The DAC txen signals are connected to different pins
  * The polarity of the spi_en signal is active low instead of active high
  * The maximum lane rate is up to 15.4 Gpbs

To accommodate this all 4 possible txen signals as well as the spi_en
signal are connected to GPIOs. Software can decide how to use them
depending on which FMC board is connected.

Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
  * A10SoC: 14.2 Gbps
 2019-06-06 11:45:05 +03:00