Commit Graph

39 Commits (7ec4c00f9f89e237a6f6c9b8296099f58bdbb653)

Author SHA1 Message Date
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Istvan Csomortani a679251d7d Makefiles: Update Make 2015-09-09 17:13:19 +03:00
Rejeesh Kutty fb648ab6f5 moved to qsys 2015-07-23 15:26:21 -04:00
Rejeesh Kutty 3ccf1bef36 base system modifications 2015-07-23 15:23:10 -04:00
Adrian Costina a7da779b94 Makefile: Updated Makefiles 2015-07-16 18:19:42 +03:00
Rejeesh Kutty 4e99a2cb01 xcvr: remove signal tap 2015-07-16 08:09:56 -04:00
Rejeesh Kutty a454b73d27 fmcjesdadc1/a5gt: split xcvr cores 2015-07-15 09:44:53 -04:00
Rejeesh Kutty 226e23ca1f fmcjesdadc1- xcvr components 2015-07-15 09:44:51 -04:00
Rejeesh Kutty f64df40a0a signal tap removed 2015-07-08 15:47:50 -04:00
Rejeesh Kutty 19bf05c740 signal tap removed 2015-07-08 15:47:48 -04:00
Rejeesh Kutty bbf1c5b803 transceiver core added/gpio removed 2015-07-07 15:30:38 -04:00
Istvan Csomortani 46fa91d5be Makefile: Update Make files 2015-07-03 18:08:57 +03:00
Rejeesh Kutty 18e8914087 fmcjesdadc1/a5gt: pn-errors version 2015-07-01 13:43:12 -04:00
Rejeesh Kutty 35aca98b5f fmcjesdadc1/stap: added 2015-07-01 13:43:10 -04:00
Rejeesh Kutty 330c205e8e fmcjesdadc1- sys_clk changes 2015-06-30 10:47:21 -04:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty 543e08b67a fmcadc1: sdc updates 2015-06-25 04:25:39 -04:00
Rejeesh Kutty 15740a7d34 fmcjesdadc1- 15.0 updates 2015-06-24 05:31:09 -04:00
Rejeesh Kutty f81d22a17a altera- common timing check 2015-06-04 10:56:32 -04:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Adrian Costina 1c9b41db6f fmcjesdadc1: A5GT project, added modular sgdma for Ethernet, nios configured for linux 2015-05-08 14:51:24 +03:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina 374f82e7de makefiles: The clean command for library won't remove the xml files, except for component.xml.
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Adrian Costina 780455d68c Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Rejeesh Kutty 0a8823361f fmcjesdadc1/a5gt: 14.1 updates 2015-04-03 14:54:57 -04:00
Rejeesh Kutty 3aac5f9494 fmcjesdadc1/a5gt: 14.1 updates 2015-04-03 14:54:55 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty b7d72a5b2e makefile: added 2015-04-01 16:29:16 -04:00
Adrian Costina 9672271155 fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
2015-01-23 13:30:56 +02:00
Adrian Costina 6ac774a9dd fmcjesdadc1: Update altera system_timing script 2014-12-10 17:53:29 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Rejeesh Kutty cb29b83b05 a5gt: updates to match a5gt 2014-08-25 10:46:59 -04:00
Rejeesh Kutty 33979fc533 fixes to improve timing - fifo for clock domain transfers 2014-04-04 13:49:53 -04:00
Rejeesh Kutty 6a19b34a00 a5gt: added tightly coupled memory 2014-04-03 20:50:17 -04:00
Rejeesh Kutty 12e5cc91bd make signaltap/timing part of the flow 2014-04-03 20:50:15 -04:00
Rejeesh Kutty e85153b5dd altera hal version 2014-04-01 21:12:11 -04:00
Rejeesh Kutty 04df908fbf altera-fmcjesdadc1 initial checkin 2014-04-01 12:01:57 -04:00
Rejeesh Kutty 0d678b89ed altera a5gt fmcjesdadc1 setup 2014-04-01 11:46:37 -04:00