d18f6aa816
adrv9371x: A10GX, added adcfifo
...
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
5cc2ab37a5
version_upgrade: Common ZC702 get an upgrade to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 10:20:04 +03:00
cd0c981b50
projects/scripts: Fix to prevent a warning
...
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
2016-08-26 10:08:00 +03:00
6ab137a0e9
projects/scripts: Cosmetics
2016-08-26 10:07:08 +03:00
9dfcfe6146
version_upgrade: adv7511 common script to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 09:52:01 +03:00
264bde77ad
sdrstk- SWAP==1 option
2016-08-24 12:07:13 -04:00
3c6cfdc7b5
adrv9371x: A10GX, switched TX lanes
2016-08-24 18:06:14 +03:00
215edb11c6
adrv9371: A10GX, updated design
...
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
320f87d63b
sdrstk- fix spi/port connections
2016-08-22 16:52:43 -04:00
270f8a6bbe
adrv9371x: Updated project common
2016-08-22 16:58:21 +03:00
f1b834ab25
scripts: Update script so that all interconnects are optimized for performance
2016-08-22 16:56:02 +03:00
c6b065c349
zc706: Updated DDR3 dacfifo
2016-08-22 16:48:52 +03:00
f697490de6
hdlmake- updates
2016-08-19 15:59:41 -04:00
5c35012f54
sdrstk- updates
2016-08-19 15:59:13 -04:00
8582517712
sdrstk- updates
2016-08-19 15:56:48 -04:00
67bf8f8e78
scripts- fix path and device defaults and override
2016-08-19 15:56:07 -04:00
6ef9555909
sdrstk- added
2016-08-19 13:45:40 -04:00
41203d07e9
adrv9371x: A10GX, update SPI connection
2016-08-18 17:42:27 +03:00
10b9a0e52f
upadated xcvr ips
2016-08-17 15:51:55 -04:00
03c83b59bf
adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm
2016-08-17 19:03:53 +03:00
5d0e08d92e
common/vc707- 2016.2 version
2016-08-17 10:36:19 -04:00
73413366bc
daq2/all - warnings fix
2016-08-17 10:36:00 -04:00
0b6fbf2208
daq2/vc707- 2016.2 updates
2016-08-17 10:34:06 -04:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
0694a5015d
kc705- 2016.2 version
2016-08-16 12:54:39 -04:00
8311098384
daq2/kc705- adxcvr changes
2016-08-16 12:54:39 -04:00
8464816c82
dmafifo-split to adc/dac
2016-08-16 12:54:39 -04:00
6a8ca8107a
common: Added common ad_dcfilter stub for altera.
2016-08-16 17:37:16 +03:00
eb55f600fb
adrv9371x: Initial commit
...
-need to fix dc filter module for AD9371 / altera
2016-08-16 15:50:46 +03:00
5c27ccd1fa
adrv9371x: Added common qsys tcl
2016-08-16 15:34:10 +03:00
4658686ae1
adrv9371x/a10soc: Misc changes for being able to run Linux
2016-08-16 11:56:25 +03:00
e754f0a46a
up_axi- writes dropped by delayed w-responses
2016-08-14 11:21:19 -04:00
39c1c83d00
adrv9371x/a10soc: Fix spi_csn assignment
2016-08-12 10:07:11 +03:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
5d93e542ed
daq2-kcu105: 2016.2 updates
2016-08-11 10:00:41 -04:00
16ad0f4379
kcu105- 2016.2 update
2016-08-11 10:00:41 -04:00
3427965cd2
adxcvr- add u-gth bufg
2016-08-11 10:00:41 -04:00
bb9cb86f34
adc/dac- fifo constraints
2016-08-11 10:00:41 -04:00
829e4155ca
modified transceiver configuration files
2016-08-10 14:59:38 -04:00
b8f4e1c0aa
updated 9680 hdl files(to resolve a critical warning)
2016-08-10 14:50:31 -04:00
285059aed0
kcu105: Don't use phy reset automation, as it's not supported for KCU105
2016-08-09 10:19:57 +03:00
452d4706d3
kcu105: Update base project to 2015.4.2
...
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
c6f4def93d
altera- make mmu a make switch
2016-08-08 11:54:51 -04:00
ccf1c56b33
util_upack: Patch up the description of Altera IP
2016-08-08 16:39:56 +03:00
e9ac4a5a0e
util_rfifo: Patch up the description of Altera IP
2016-08-08 16:39:25 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
aad8c265bc
lib_refactoring: Fix path for CMOS sources
2016-08-08 15:07:54 +03:00
1d33d7d7ee
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
2016-08-08 15:07:42 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
90ac7b7ac9
lib_refactoring: Move all Altera module to library/altera/common
...
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Shrutika Redkar
dbogdan