Commit Graph

1318 Commits (801da3cb25769f8e2db883229892d465067c6147)

Author SHA1 Message Date
Istvan Csomortani 977e6d9189 adi_ip_alt: Fix some typo 2016-12-06 15:24:21 +02:00
Istvan Csomortani 7876c8ffa4 axi_ad9684: Add loaden and phase ports for altera support 2016-12-06 15:24:20 +02:00
Istvan Csomortani a7d3df8757 axi_ad9684: Update hw tcl script for altera 2016-12-06 15:24:20 +02:00
Istvan Csomortani b0a5be8565 axi_ad9122: Add loaden port for altera support 2016-12-06 15:24:20 +02:00
Istvan Csomortani cedca30cd6 axi_ad9122: Update hw tcl script for altera 2016-12-06 15:24:19 +02:00
Istvan Csomortani 0715c962f1 altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in 2016-12-06 15:24:19 +02:00
Istvan Csomortani 6cf9df50e3 altera/ad_serdes: Define DEVICE_FAMILY in hw script 2016-12-06 15:24:18 +02:00
Istvan Csomortani 8b8c37e2e2 scripts/adi_ip: Remove AXIMM inference from adi_ip_infer_interfaces
The AXI Memory Map interface is infered in the adi_ip_properties process.
Infer it again in the adi_ip_infer_interfaces brakes the flow,
the tool will not find the cell's address segment, so there will not be
any address space assigned to the AXI interface.
Affected cores were axi_i2s_adi and axi_spdif_tx.
2016-12-05 14:33:39 +02:00
Lars-Peter Clausen 753f4bd06e axi_intr_monitor: Slightly modify counter start points
Start the counter_to_interrupt_cnt counter when the counter_to_interrupt
value is written to the register map. This gives applications better
control over when the counter starts counting.

Also start the counter_from_interrupt on the rising edge of the interrupt
signal to avoid bogus values.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-12-02 20:09:29 +01:00
Lars-Peter Clausen 334ce5ddc0 axi_intr_monitor: Fully register IRQ output signal
The IRQ signal goes to a asynchronous domain. In order to avoid glitches to
be observed in that domain make sure that the output signal is fully
registered.

This means that the IRQ signal is no longer mask when the control enable
bit is not set. Instead modify the code to clear the interrupt when the
control enable bit is not set. This turns it into a true reset for the
internal state.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-12-02 19:28:13 +01:00
Rejeesh Kutty 170c781d02 hdlmake.pl- updates 2016-12-01 13:52:11 -05:00
Rejeesh Kutty 95a2e02800 library/makefile- updates 2016-12-01 13:47:02 -05:00
Adrian Costina 609b01f9e4 util_clkdiv: Added division by 2 option 2016-11-24 16:01:37 +02:00
Adrian Costina 91ee4394e4 axi_intr_monitor: Initial commit 2016-11-24 15:19:36 +02:00
Istvan Csomortani f03675cdab axi_dmac: ID_WIDTH must be clog2(FIFO_SIZE*2) 2016-11-24 13:20:45 +02:00
Istvan Csomortani c705623101 axi_dmac: Fix port connection and port width mismatch 2016-11-24 12:01:45 +02:00
Rejeesh Kutty 862bd7ef2c daq3/zc706- xcvr changes 2016-11-23 15:02:20 -05:00
Rejeesh Kutty 025420d6f8 library/axi_xcvrlb- xcvr changes 2016-11-23 12:00:13 -05:00
Rejeesh Kutty 8f562fd069 xcvr updates- board procedure 2016-11-22 14:43:36 -05:00
Rejeesh Kutty 2ea997c3d5 interfaces- remove channel based pll reset 2016-11-22 11:34:29 -05:00
Rejeesh Kutty 3dbed492b3 util_adxcvr: expose cpll/qpll as it is 2016-11-22 11:32:37 -05:00
Rejeesh Kutty 3cbe735bd8 util_adxcvr: regenerate from script 2016-11-22 11:21:04 -05:00
Rejeesh Kutty c57ffc9364 axi_adxcvr- separate pll reset from channels 2016-11-22 11:12:54 -05:00
Istvan Csomortani b9795c7033 xilinx/util_adxcvr: Update enablement dependencies 2016-11-22 17:33:40 +02:00
Lars-Peter Clausen 2f2570fcac axi_i2s: Remove incorrectly inferred interfaces
Remove interfaces that were incorrectly inferred by the tools.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:29 +01:00
Lars-Peter Clausen 43c74bf55c axi_i2s: Tie-off optional inputs
Tie-off all optional inputs to 0 so that they are driven to a defined value
when not used.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:26 +01:00
Lars-Peter Clausen 26907ef1fd axi_i2s: Remove duplicated clock interface association
The I2S interface has a clock associated to it twice, this will generate a
critical warning when using the core, so remove one of them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 15:01:24 +01:00
Rejeesh Kutty b85a282748 fmcomms11- lane swap 2016-11-16 10:26:47 -05:00
AndreiGrozav 9d6c93a5d8 Fix warnings 2016-11-14 15:17:15 +02:00
Istvan Csomortani 12d6e46ae7 clean: Delete deprecated source files
The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located
at library/xilinx and library/altera.
The axi_jesd_xcvr was an early version of axi_adxcvr.
The register map is moved to the IP's directory.
2016-11-14 10:43:46 +02:00
Adrian Costina c80033cb1b util_fir_int: removed s_axis_data_tvalid and updated sdrstk 2016-11-11 17:52:19 +02:00
Adrian Costina 6f4dc92dd2 util_fir_int: Fix channel data assignment 2016-11-11 15:46:17 +02:00
Adrian Costina 64d1d54ec0 util_fir_int: Update filter, as it's used with ad9361 in CMOS mode 2016-11-10 17:45:03 +02:00
Adrian Costina 66098b7ae7 util_fir_dec: Update filter, as it's used with ad9361 in CMOS mode 2016-11-10 17:43:04 +02:00
Istvan Csomortani 6073cdded4 axi_ad9250: Tie rx_valid to ground 2016-11-10 10:52:37 +02:00
Istvan Csomortani 8845aeb6ab axi_ad9250: Add missing file to Make and script 2016-11-10 10:48:46 +02:00
Istvan Csomortani 8493bd4329 axi_ad6676: Update the core, sof interface added 2016-11-10 10:39:33 +02:00
Rejeesh Kutty 0b58a2a1db avl_adxcvr- sysclk frequency 2016-11-09 09:21:07 -05:00
Rejeesh Kutty 48ee720901 avl_adxcvr- a5 requires single transceiver controller 2016-11-08 15:20:01 -05:00
Rejeesh Kutty a58597c13a ad9250 - build fixes 2016-11-08 15:17:54 -05:00
Rejeesh Kutty d7357d781b axi_ad9250 - avalon/axi streaming + sof 2016-11-04 15:30:39 -04:00
Rejeesh Kutty ee9c8b884d avlxcvr- add arria v support 2016-11-04 15:01:19 -04:00
Adrian Costina 9dc7f16d80 axi_usb_fx3: Added zero length packet capability 2016-11-03 15:29:56 +02:00
Rejeesh Kutty 1e0fed82f7 alt_serdes- a10 ddio fixes 2016-11-01 12:41:25 -04:00
Istvan Csomortani 5eff357568 up_tdd_cntrl: Fix memory map register writes 2016-11-01 10:06:57 +02:00
Rejeesh Kutty 9f4c5f8060 arradio/ad9361- updates 2016-10-31 15:34:32 -04:00
Rejeesh Kutty b94cc8afb1 altera- cmos cores 2016-10-31 13:13:48 -04:00
Rejeesh Kutty e0459df0f3 altera -c5 qsys alternative 2016-10-31 11:18:27 -04:00
Rejeesh Kutty cc75fa3dfe altera- java/tcl mess handling 2016-10-31 10:54:07 -04:00
Rejeesh Kutty a9d03af771 altera- serdes changes 2016-10-28 14:09:18 -04:00