1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
ac2e5a9dac
constraints: Update constraints
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Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
343d0472d4
fmcadc2: Move GT setting to common/system_bd.tcl
2017-02-16 14:56:25 +02:00
07184b31d2
fmcadc2: Define default clock selection for Xilinx GTs
2017-02-16 12:35:24 +02:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
0c42e04bc3
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
c455d2d64f
fmcadc2/vc707: Disabele axi_spi constraint file
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The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:15:44 +02:00
3dceb53984
fmcadc2/vc707: Fix timing violations
2016-12-08 19:51:18 +02:00
8eaae98728
fmcadc2: Updates
2016-12-07 21:43:19 +02:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
aff45eae5f
fmcadc2: xcvr updates
2016-11-21 18:45:38 +02:00
93fa5aeec3
fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
2016-09-01 16:11:39 +03:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
be74db656c
ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
...
Update system_project.tcl scripts to correctly select the necessary
constraint files
2016-05-04 19:37:33 +03:00
3ca3414522
fmcadc2: Fixed bus data width
2016-05-04 19:20:01 +03:00
9104b2cc60
ad6676evb, fmcadc2, fmcadc4, fmcadc5,...
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ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
2016-05-04 19:13:25 +03:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
9cd0378003
fmcadc2: Added clock constraint for the ADC path
2016-01-22 15:44:04 +02:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
848b51699c
fmcadc2: Updated VC707 project
2015-09-25 17:28:15 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
6b9906b22b
Refresh Makefiles
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Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
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Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
91279253ef
Makefiles: Added mig project file as a dependency for Microblaze based projects. Also updated usdrx1 a5gt Makefile
2015-05-08 15:31:40 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
bb185296d7
fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples.
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The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
2015-04-23 18:00:00 +03:00
a61a195e3f
Makefiles: Updated makefiles to add the new constraints as dependecies
2015-04-23 11:16:39 +03:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
8b5d1a8693
fmcadc2: Connect the second CS line for the external SPI interface
2015-04-15 19:08:17 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
4f7f109056
util_adcfifo: added
2015-04-07 16:08:38 -04:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
ae960e66e9
makefile: added
2015-04-01 16:29:07 -04:00
8bc589a4d4
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:17 -04:00
a24c1d33e9
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:15 -04:00
86512ad95a
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:10 -04:00
19e4950b72
renamed to match official names
2014-12-08 10:44:15 -05:00
Istvan Csomortani
Rejeesh Kutty
AndreiGrozav
Adrian Costina
Lars-Peter Clausen