ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
67390c2a95
ad6676evb: Update projects with ad_sysref_gen
2016-12-19 10:52:25 +00:00
557efed5d9
ad6676evb: Update clock constraints
2016-12-14 17:55:49 +02:00
d6918de19e
ad6676: Update projects to xcvr frame work
2016-11-10 10:39:46 +02:00
dca39c26f9
ad6676evb: Added clock constraint for the ADC path
2016-01-22 15:45:16 +02:00
ab4b73fd32
ad6676evb: Updated VC707 project
2015-09-25 16:07:22 +03:00
7f2cc2117c
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
3211964c2e
ad6676evb: added
2014-11-10 13:41:01 -05:00
Istvan Csomortani
Adrian Costina
Rejeesh Kutty