Commit Graph

45 Commits (80a3f45b9f855f8f15503d226d8fdd350b1f664e)

Author SHA1 Message Date
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty fb4a583613 projects/system_bd- adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Istvan Csomortani 5fa6dba333 Make: Update Makefiles 2017-02-10 16:32:58 +02:00
Istvan Csomortani f47863bbcf usdrx1: Integrate ad_syref_gen into the project 2016-12-19 14:36:01 +00:00
AndreiGrozav d962614000 usdrx1/zc706: Disabele axi_spi constraint file
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:23:51 +02:00
Adrian Costina 284fbac571 usdrx1: Xcvr updates, so that the channel parameters are correctly configured from boot time 2016-11-28 14:16:07 +02:00
Adrian Costina 7c541c704a usdrx1: ZC706, Update project to the new GT framework 2016-10-14 18:08:08 +03:00
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
Istvan Csomortani b0538a03a2 Make: Update 2016-05-06 16:44:24 +03:00
Istvan Csomortani 4863a04132 axi_adc/dacfifo: Split the intergration script file
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
2016-05-05 09:53:55 +03:00
Rejeesh Kutty 385ed31a45 make files update 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 3006c5a223 make updates 2016-04-11 16:14:59 -04:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Adrian Costina 88e8bef92f usdrx1: Update ZC706 project 2015-10-09 13:33:45 +03:00
Istvan Csomortani a679251d7d Makefiles: Update Make 2015-09-09 17:13:19 +03:00
Lars-Peter Clausen 9fb336e464 usdrx1: Add DDR FIFO
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.

Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.

Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Adrian Costina a7da779b94 Makefile: Updated Makefiles 2015-07-16 18:19:42 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Rejeesh Kutty 4927ca85c2 projects- jesd-align port name change 2015-05-20 14:24:26 -04:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Adrian Costina 949abcdc8f Makefile: Updated makefiles so that the project recipe does not depend on lib 2015-05-06 14:58:29 +03:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina 780455d68c Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty 0184d2a4c7 makefile: added 2015-04-01 16:30:05 -04:00
Adrian Costina 037484e1d0 usdrx1: Updated project to the latest framework 2015-03-25 17:39:51 +02:00
Istvan Csomortani 4ea86de4db usdrx1_zc706: Update interrupts. 2014-11-27 14:03:54 +02:00
Adrian Costina a0d27a117c usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints 2014-10-22 13:20:44 +03:00
acostina 5af2474d51 usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization 2014-09-23 22:44:33 -04:00
Adrian Costina bdf01738a1 ultrasound: disconnected ADN4670 chips from SPI lines.
Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
2014-09-23 22:30:42 -04:00
Adrian Costina d33fb07587 usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
GPIOs for which the directions is known, have been specifically assigned.

The SPI clock has been changed to a lower frequency.
2014-09-16 15:56:19 -04:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Adrian Costina a773cc4992 usdrx1: updated project
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
Rejeesh Kutty 38126c404c usdrx1: spi signal definitions 2014-04-11 14:28:23 -04:00
Rejeesh Kutty 06b28d2e24 ad9671: compile fixes 2014-04-11 14:28:22 -04:00
Rejeesh Kutty 96541f0a7f usdrx1: zc706 updated for usdrx1 2014-04-10 11:05:13 -04:00
Rejeesh Kutty ac1c145a61 usdrx1: initial checkin 2014-04-10 11:05:10 -04:00